Assignment 01

NAME: Fuldeore Srushti Vinod SUBJECT: COA

ID: 201071908 BRANCH: Computer

Q.1 Write short note on computer designing for performance.

Solution:-
Computer performance is the amount of work accomplished by a computer system.
The word performance in computer performance means “How well is the computer
doing the work it is supposed to do?” It basically depends on response time,
throughput and execution time of a computer system.
Computer designing for performance:
Factors behind the need of computer for designing purpose:
1. Speeding up the performance
 Pipelining
 On board cache
 On board L1 & L2 cache
 Branch prediction - The processor looks ahead in the instruction code
fetched from memory and predicts which branches, or groups of
instructions, are likely to be processed next. If the processor guesses right
most of the time, it can prefetch the correct instructions and buffer them
so that the processor is kept busy
 Data flow analysis - The processor analyzes which instructions are
dependent on each other’s results, or data, to create an optimized schedule
of instructions. In fact, instructions are scheduled to be executed when
ready, independent of the original program order. This prevents
unnecessary delay
 Speculative execution - Using branch prediction and data flow analysis,
some processors speculatively execute instructions ahead of their actual
appearance in the program execution, holding the results in temporary
locations. This enables the processor to keep its execution engines as busy
as possible by executing instructions that are likely to be needed.
2. Performance Balance
 Processor speed increased
 Memory capacity increased
 Memory speed lags behind processor speed
3. There are a number of ways that a system can increase its performance
 Increase the number of bits that are retrieved at one time by making
DRAMs “wider” rather than “deeper” and by using wide bus data paths.
  Change the DRAM interface to make it more efficient by including a
cache7 or other buffering scheme on the DRAM chip.
 Reduce the frequency of memory access by incorporating increasingly
complex and efficient cache structures between the processor and main
memory.
 Increase the interconnect bandwidth between processors and memory by
using higher-speed buses and by using a hierarchy of buses to buffer and
structure data flow.

Q.2 Explain floating point addition and multiplication.

Solution:-
Floating point numbers are numbers that contain floating decimal points.
For example, the numbers 5.5, 0.001, and -2,345.6789 are floating point numbers.

Fig. Typical 32-Bit Floating-Point Format

Example:
1.1010001 * 210100 = 0 10010011 10100010000000000000000 = 1.6328125 * 210
–1.1010001 * 210100 = 1 10010011 10100010000000000000000 = –1.6328125 * 220
For each example, on the left is the binary number; in the center is the corresponding
bit pattern; on the right is the decimal value.
Note the following features:
• The sign is stored in the first bit of the word.
• The first bit of the true significant is always 1 and need not be stored in the
significant field.
• The value 127 is added to the true exponent to be stored in the exponent field.
• The base is 2
Floating point addition:
The two significant are added together, taking into account their signs. Because the
signs may differ, the result may be 0. There is also the possibility of significant overflow
by 1 digit. If so, the significant of the result is shifted right and the exponent is
incremented. An exponent overflow could occur as a result; this would be reported and
the operation halted.
Steps:
1. Check for zeros
2. Align significant (adjusting exponents)
3. Add or significant
4. Normalize result

Example

Perform 0.5 + (-0.4375)

0.5 = 0.1 × 20 = 1.000 × 2-1 (normalised)

-0.4375 = -0.0111 × 20 = -1.110 × 2-2 (normalised)

1. Rewrite the smaller number such that its exponent matches with the exponent of
the larger number.

-1.110 × 2-2 = -0.1110 × 2-1

2. Add the mantissas:

1.000 × 2-1 + -0.1110 × 2-1 = 0.001 × 2-1

3. Normalise the sum, checking for overflow/underflow:

0.001 × 2-1 = 1.000 × 2-4

-126 <= -4 <= 127 ===> No overflow or underflow

4. Round the sum:

The sum fits in 4 bits so rounding is not required

Floating point multiplication:

Steps:
1. Check for zero
2. Add/subtract exponen
3. Multiply/divide significant (watch sign)
4. Normalize
5. Round
6. All intermediate results should be in double length storage
Example

1.110 × 1010 × 9.200 × 10-5

1. Add the exponents to find

New Exponent = 10 + (-5) = 5

If we add biased exponents, bias will be added twice. Therefore we need to

subtract it once to compensate:

(10 + 127) + (-5 + 127) = 259

259 - 127 = 132 which is (5 + 127) = biased new exponent

2. Multiply the mantissas

1.110 × 9.200 = 10.212000

Can only keep three digits to the right of the decimal point, so the result is

10.212 × 105

3. Normalise the result

1.0212 × 106

4. Round it

1.021 × 106

Q.3 what is the difference between interrupt service routine and subroutine?
Solution:-
Interrupt Service Routine Subroutine
Initiated by some external or internal Initiated by execution of some
signal instruction
Address of the interrupt service routine Address of the subroutine determined
determined by hardware from the address part of the instruction
Interrupt procedure stores all
Only the value of the PC stored before
information to describe the state of the
branching to the subroutine
CPU
 Call occurs at specific and
Can ask for service without any prior
predetermined locations in the main
notice
routine.
Hardware initiated Software initiated
Request can come unexpectedly; may
have to carry out some emergency
Request can come expectedly
activities-like saving the status of scratch
pad registers.

Q.4 Explain bus interconnection. Write short note on bus arbitration.

Solution:-
Bus interconnection:
 A bus is a communication pathway connecting two or more devices.
 A key characteristic of a bus is that it is a shared transmission medium. Multiple
devices connect to the bus, and a signal transmitted by any one device is available
for reception by all other devices attached to the bus.
 A bus consists of multiple communication pathways, or lines. Each line is
capable of transmitting signals representing binary 1 and binary 0
 Computer systems contain a number of different buses that provide pathways
between components at various levels of the computer system hierarchy.
 A bus that connects major computer components (processor, memory, I/O) is
called a system bus
Architecture of Bus Interconnection:

 Data lines- The data lines provide a path for moving data among system
modules. These lines, collectively, are called the data bus. The data bus may
consist of 32, 64, 128, or even more separate lines, the number of lines being
referred to as the width of the data bus. Because each line can carry only 1 bit at
a time, the number of lines determines how many bits can be transferred at a
time.
 Address lines- The address lines are used to designate the source or destination
of the data on the data bus. For example, if the processor wishes to read a word
(8, 16, or 32 bits) of data from memory, it puts the address of the desired word
 on the address lines. Clearly, the width of the address bus determines the
maximum possible memory capacity of the system.
 Control lines- The control lines are used to control the access to and the use of
the data and address lines. Because the data and address lines are shared by all
components, there must be a means of controlling their use. Control signals
transmit both command and timing information among system modules. Timing
signals indicate the validity of data and address information. Command signals
specify operations to be performed.

Bus arbitration:
 It is the process of determining which competing bus master will be permitted
access to the bus.
 It is the process by which the next device to became the bus master is selected
and bus master ship is transferred to it.
 Arbitration is the process where more than one module is controlling the bus.
 Examples:
1. CPU and DMA controller
 Only one module may control bus system at a time
There are two types:
1. Centralized:
o It is a single hardware device for controlling the bus
o It may be a part of CPU
o The processor is normally the bus master unless it grants bus membership to
one of the DMA controller.
2. Decentralized:
o Each module may claim the bus control unit logic is presentation own module.
o Offer high reliability
o Operation of bus is not dependent on single device