SUBJECT CODE : EC8552

Strictly as per Revised Syllabus of

Anna University
Choice Based Credit System (CBCS)
Semester - V (ECE)

Computer Architecture
& Organization

Atul P. Godse
M.S. Software Systems (BITS Pilani)
B.E. Industrial Electronics
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology
Pune

Dr. Deepali A. Godse

M.E., Ph.D. (Computer Engg.)
Head of Information Technology Department,
Bharati Vidyapeeth's College of Engineering for Women,
Pune

® ®

TECHNICAL
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge

(i)
Computer Architecture
& Organization
Subject Code : EC8552

Semester - V (Electronics & Communication Engineering)

First Edition : June 2019

Second Revised Edition : June 2020

ã Copyright with Authors

All publishing rights (printed and ebook version) reserved with Technical Publications. No part of this book
should be reproduced in any form, Electronic, Mechanical, Photocopy or any information storage and
retrieval system without prior permission in writing, from Technical Publications, Pune.

Published by :
® ®
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TECHNICAL Pune - 411030, M.S. INDIA, Ph.: +91-020-24495496/97
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge Email : sales@[Link] Website : [Link]

Printer :
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Tal. - Haveli, Dist. - Pune - 411041.

ISBN 978-93-332-0212-1

9 789333 202121 AU 17

9789333202121 [2] (ii)

 Memory unit

Arithmetic
and
Input Logic Unit Output
unit unit
Control
unit
 Software

System software Application software

Examples :  Operating system Examples :  Word processors
 Device drivers  Spreadsheets
 Language translators  Image editors
 System utilities  Database management systems
 Presentation application
 Desktop publishing software
 Printer

Disk

OS
routines

Program

Time
t0 t1 t2 t3 t4 t5
1 2 3 4 5
Steps :
Time line diagram

t0 t1

t1 t2
 t2 t3

t3 t4

t4 t5

t5

t4 t5

t0 t1
 Processor

R0 PC

R1
ALU
R2
IR Control
unit

Rn
MDR MAR

General purpose
registers

Main memory
 1
Performance A
Execution time A

Performance A Performance B
1 1
Execution time A Execution time B

Execution time B Execution time A

Performance A
Performance B

Performance A Execution time B

 n
Performance B Execution time A

Performance A Execution time B

 n
Performance B Execution time A

15
10

Performance A
Performance B
 Performance A
Performance B
1.5

CPU execution time for a program = CPU clock cycles for a program  Clock cycle time
 CPU clock cycles for a program
CPU execution time for a program
Clock rate

rateA 3  10 9 cycles sec

time A
time B

CPU clock cycles A

CPU time A
Clock rate A

CPU clock cyclesA

12 seconds
3  10 9 cycles sec

 CPU clock cyclesA 12 seconds  3  10 9 cycle sec 36  10 9 cycles

CPU clock cycles B 1.2  CPU clock cyclesA

time B
Clock rate B Clock rate B
1.2  36  10 9 cycles

Clock rate B
1.2  36  10 9 cycles
Clock rate B 4.8 cycles sec  4.8 GHz
9 seconds
 2  10 9

  

 20  10 9

 20  10 9 0.2 20  10 9

4  10 9

N  CPI N  CPI
N  CPI  Clock cycle time
R Clock rate

CPU clock cycles

Instruction count

clocks second
 CPU clock cyclesA N  2.0 CPU clock cycles B N  1.2

CPU time A CPU clock cyclesA  Clock cycle timeA

N  2.0  250 ps  500 N ps
CPU time B CPU clock cycles B  Clock cycle time B
N  1.2  500 ps  600 N ps

CPU Performance A Execution times B 600 N ps

  1.2
CPU Performance B Execution timesA 500 N ps
 4  2  4  10 instructions
8  2  2  12 instructions

(4  1)  (2  2)  (4  3)
(8 1)  (2  2)  (2  3)

CPU clock cycles

Instruction count
20 18
 CPI 1  2.0 CPI 2  1.5
10 12
 3  10 9
2  10 9
1.5
2.5  10 9
2.5 10 9
1.0
4.0  10 9
1.82 10 9
2.2

10 3  10 9 30  10 9

10  2.5  10 9 25 10 9
 10  4.0  10 9 40  10 9

(Number of instructions  CPI)

Clock rate

Time  Clock rate Number of cycles


CPI CPI
30  10 9
20  10 9
1.5
25 10 9
25 10 9
1.0
40  10 9
18.18 10 9
2.2

1.0  10 6

105 2  105 5  105

2  105

(105  2  105  2  5  105  3  2  105  3) (2.5  10 9 ) 10.4  10  4 S

(105  2  2  105  2  5  105  2  2  105  2) (3  10 9 ) 6.66  10  4 S

10.4  10 4  2.5  10 9 10 6

6.66  10 4  3  10 9 10 6

105  1  2  105  2  5  105  3  2  105  3 26  105

105  2  2  105  2  5  105  2  2  105  2 20  105

 10000
3600 120
2000 2667
1000 100
103
Clock rate 95
80
Clock 100 66 Power
200 75.3 60
rate 16 25 (watts)
(MHz) 12.5 40
10
10.1 29.1
3.3 4.1 4.9 20
1 0
80286 80386 80486 Pentium Pentium Pentium 4 Pentium 4 Core 2
(1982) (1985) (1989) (1993) Pro Willamette Prescott Kentsfield
(1997) (2001) (2004) (2007)
 Voltage 2

CV2 f

85 %
20 % 25 %

Power (new processor) (C  0.85)  (V  0.8) 2  (f  0.75)

Power (old processor) CV2 f

(0.85)  (0.8) 2  (0.75)

40.8 %
Instruction

R
Registers

Operand

Instruction

Address
Memory

Operand
 Instruction

Operand

Instruction
Address

Memory

Operand

Instruction
R

Registers Memory

Operand
 Instruction
R Value

Registers Memory

Operand
 op rs rt rd  funct
Registers
Register

op rs rt Address
Memory

Register + Byte Halfword Word

op rs rt Address

Memory

PC + Word

op Address

Memory

PC + Word

Opcode Offset

XXXX 00
Opcode Operand address1 Operand address2

4-bits 6-bits 6-bits

 

Y  ( A  B) * (C  D)

























 

216
 MSB LSB
1 0 1 1 0 0 1 1 0

0 1 1 0 0 1 1 0

(a) Left logical shift

MSB LSB
1 0 1 1 0 0 1 1

0 0 1 0 1 1 0 0 1

(b) Right logical shift

MSB LSB
1 0 1 1 0 0 1 1 0

0 1 1 0 0 1 1 0

(a) Left arithmetic shift

MSB LSB
1 0 1 1 0 0 1 1

1 1 0 1 1 0 0 1

(b) Right arithmetic shift

 2n

2n
B 31 - 26 B25 - 21 B20 - 16 B15 - 11 B10 - 6 B5 - 0
B 31 - 26 B25 - 21 B20 - 16 B15 - 0
B 31 - 26 B25 - 0

.
CPU execution time for a program = CPU clock cycles for a program  Clock cycle time

CPU clock cycles for a program

CPU execution time for a program
Clock rate
.

1
Average time required for the execution of instruction  10 6

N R
C  10 6

Running time on the reference computer

Running time on the computer under test


 Memory

Register
(1000) H
1000H 1000H Operand
1001H
1002H Array
 
 
 
 Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

k k k k k k k k k k
2 –4 2 –4 2 –3 2 –2 2 –1 2 –4 2 –1 2 –2 2 –3 2 –4

(a) Big-endian assignment (b) Little-endian assignment

3  16 3  8  16 2  3  16 1  4  16 0
3  16 3  2  16 2  3  16 1  9  16 0
9  16 3  2  16 2  4  16 1  8  16 0

B7 B6 B5 B4 B3 B2 B1 B0

Sign Magnitude
 Maximum positive number : 0 1 1 1 1 1 1 1 = +127
Maximum negative number : 1 1 1 1 1 1 1 1 = –127

1 1 0 1 0 1 0 0 Number

NOT operation

0 0 1 0 1 0 1 1 1's complement of number

1 1 0 0 0 1 0 0 Number

1 1 Carry
0 0 1 1 1 0 1 1 1's complement of number
+ 1 Add 1
0 0 1 1 1 1 0 0 2's complement of number
 (10101100) 2 ( 01010011) 2
( 01011011) 2 (10100101) 2

 
 

1 1 Carry
0 1 1 0 = (6)10
0 1 1 1 = (7)10
1 1 0 1 = (13)10
 A Carry
Inputs Half Outputs
adder
B Sum

B B
A 0 1 A 0 1

0 0 0 0 0 1 A
Sum
B
1 0 1 1 1 0
Carry

Carry = AB Sum = AB + AB
=A+B
 Cin

A
Full
Sum
adder
B

Cout

For carry (Cout) For sum

BCin BCin
A 00 01 11 10 A 00 01 11 10

0 0 0 1 0 0 0 1 0 1

1 0 1 1 1 1 1 0 1 0

Cout = AB+A Cin+B Cin Sum = A BCin+ABCin+AB Cin+ABCin

A
A B
Cin
B A
B
A Cin
Cin Cout Sum
A
B
Cin
B
A
Cin B
Cin

A B C in  A B Cin  A B Cin  A B C in
C in (A B  AB)  Cin (A B  A B) C in (A B)  Cin (A  B)
C in (A  B)  Cin (A  B) C in  ( A  B)
 A
B Sum
Cin
B

A
C out AB  A C in  B C in A
Cout
AB  A C in (B  B)  B C in (A  A) Cin
Cin

AB  ABC in  A B C in  ABC in  A BC in B

AB (1  C in  C in )  A BC in  A BC in

AB  ABC in  ABC in AB  C in (AB  AB) AB  C in (A  B)

First half-adder Second half-adder

A Cin  (A  B)
B Sum

Cin (A  B)

Cout
Cin
AB

Bn An B2 A2 B1 A1 B0 A0

Full Cn–1 Full C2 Full C1 Full

Cn C0
adder adder adder adder

Sn–1 S2 S1 S0
 (11101100)2  (00110010)2 .
10
0 0 10 0 10
1 1 1 0 1 1 0 0 Number 1
0 0 1 1 0 0 1 0 Number 2
1 0 1 1 1 0 1 0 Result

Note : (10)2 – (1)2 = (1)2

(28)10  (15)10

(28) 10 (011100) 2
(15) 10 (001111) 2
(15)10  (28)10

(15) 10 (001111) 2 (28) 10 (011100) 2

0 0 1 1 1 1 (15)10

Carry
1 1 0 0 0 0 1's complement of (15)10

1 1 Carry (28)10
0 1 1 1 0 0 Binary equivalent of (28)10 +
+ (–15)10
Sign Extension 1 1 0 0 0 0 1's complement of 15, i.e. (–15)10
1 0 0 1 1 0 0 Result (13)10
+ 1 Add end around carry
0 0 1 1 0 1 Final result : Binary equivalent of (13)10
 0 1 1 1 0 0 Binary equivalent of (28)10

1 1 Carry
1 0 0 0 1 1 1's complement of (28)10

1 1 1 1 Carry
(15)10
0 0 1 1 1 1 Binary equivalent of (15)10 +
+ (–28)10
1 0 0 0 1 1 1's complement of (28)10
1 1 0 0 1 0 Result = Binary equivalent of (–13)10 (–13)10

Verification 0 0 1 1 0 1 1's complement of result (Binary equivalent of (13)10)

(– 4)10  (8)10

1 1 Carry
Sign 1 1 0 1 1 1's complement of 4
extension
+ 0 1 0 0 0 (8)10
1 0 0 0 1 1
+ 1 Add end around carry
0 0 1 0 0 Result

(28)10  (15)10

(28) 10 (011100) 2

(15) 10 (001111) 2
 0 0 1 1 1 1 (15)10

Carry
1 1 0 0 0 0 1's complement of (15)10
+ 1 Add 1
1 1 0 0 0 1 2's complement of 15, i.e., (–15)10

1 1 Carry (28)10
0 1 1 1 0 0 Binary equivalent of (28)10 +
+ (–15)10
Sign Extension 1 1 0 0 0 1 2's complement of 15, i.e. (–15)10
Ignore Carry 1 0 0 1 1 0 1 Result : Binary equivalent of (13)10 (13)10

(15)10  (28)10

(15) 10 (001111) 2 (28) 10 (011100) 2

0 1 1 1 0 0 Binary equivalent of (28)10

1 1 Carry
1 0 0 0 1 1 1's complement of (28)10
+ 1 Add 1
1 0 0 1 0 0 2's complement of (28)10, i.e., (–28)10

No carry 0 1 1 Carry
(15)10
0 0 1 1 1 1 Binary equivalent of (15)10 +
+ (–28)10
1 0 0 1 0 0 2's complement of (28)10
1 1 0 0 1 1 No carry, thus result is negative (–13)10
and in 2's complement form
Verification 0 0 1 1 0 0 1's complement of result
+ 1 Add 1
0 0 1 1 0 1 – Result = Binary equivalent of (13)10

(– 4)10  (– 6)10

0 1 0 0 (4)10
1 0 1 1 1's complement of 4
+ 1 Add 1
1 1 0 0 2's complement of 4

1 Carry
1 1 0 0 2's complement of 4
+ 0 1 1 0 (6)10
Discard carry 1 0 0 1 0 Result = (0 0 1 0)2
 (11010) 2 – (10000) 2

1 0 0 0 0
0 1 1 1 1 1’s complement of (10000)
+ 1
1 0 0 0 0 2’s complement of (10000)

1 1 1 1 Carry
1 1 0 1 0 (11010)2
+ 0 1 1 1 1 1’s complement of 10000
0 1 0 0 1 Result
1 Add end around carry
0 1 0 1 0 Result is + ve

1 Carry
1 1 0 1 0 (11010)2
+ 1 0 0 0 0 2’s complement of 10000
Ignore carry 1 0 1 0 1 0 Result is + ve

(11011) 2 – (10011) 2

1 0 0 1 1
0 1 1 0 0 1’s complement
0 1 1 0 1 2’s complement

1 1 1 1 1 Carry
1 1 0 1 1
+ 0 1 1 0 1 2’s complement of (10011)2
Discard carry 1 0 1 0 0 0 Result : (1000)2
 1 1 1 1 1 1 1 1 1 1 Carry
X+Y: 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 (X)
+ 1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 (Y)
1 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 Result

Y–X: X= 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1
1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 1's complement
+ 1 Add 1
1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 2's complement
1 1 1 1 1 1 Carry
1 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 Y
+ 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 (– X)
Discard 1 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 0 Result
carry

B3 A3 B2 A2 B1 A1 B0 A0

Full C3 C2 Full C1 Full

C4 Full C0=1
adder adder adder adder

S3 S2 S1 S0
 B Register
bn–1 b1 b0
Overflow
detector Add /
AVF subtract
logic
Overflow circuit control
an–1 a1 a0
Complementer

C0

n-bit adder
Parallel adder
Cn

Rn–1 R1 R0

b
b 1

an–1 an–1 bn–1 Rn–1

bn–1

Rn–1 Overflow

an–1 bn–1 Rn–1

 a n 1 b n 1 R n 1  a n 1 b n 1 R n 1

a n 1
b n 1
R n 1

1 1 1 Carry
0 1 1 1 (+ 7)
+ 0 0 1 1 (+ 3)
1 0 1 0 Result : 2's complement of 6

1 Carry
1 0 1 1 2's complement of 5, i.e. (– 5)
+ 1 1 0 0 2's complement of 4, i.e. (– 4)
0 1 1 1 (+ 7)
 1101 (13) Multiplicand
x1 0 0 1
(9) Multiplier
1101
0000
0000 Partial products
1101
1110101 Final product (117)
 Multiplicand
Bn–1 Bn–2 B1 B0
n-bit bus
n n

Add Shift and

n-Bit Adder add control
logic
n Shift Right

C An–1 An–2 A1 A0 Qn–1 Qn–2 Q1 Q0

1 bit Multiplier
Register

Note : Dotted lines indicate control signals

Start

C, A 0
B Multiplicand
Q Multiplier
Count n

Q0
No Is Yes
Q0 = 1?
Q0
C, A A+B

A n– 1
A0 Q n 1 Q0 Shift right C, A and Q
Count Count – 1
Q0

No Is
Count = 0 ?

Yes

End
 B
1 1 0 1
Initial values
C A Q
0 0 0 0 0 1 0 1 1

0 1 1 0 1 1 0 1 1 Add
First cycle
0 0 1 1 0 1 1 0 1 shift

1 0 0 1 1 1 1 0 1 Add
Second cycle
0 1 0 0 1 1 1 1 0 shift

0 1 0 0 1 1 1 1 0 No add
Third cycle
0 0 1 0 0 1 1 1 1 shift

1 0 0 0 1 1 1 1 1 Add
Fourth cycle
0 1 0 0 0 1 1 1 1 shift

Final product
 1 0 0 1 0 0 Quotient
Divisor 1 1 0 1 1 0 1 1 0 1 1 Dividend
– 1 1 0
Partial remainder 0 0 0 1 1 0
– 1 1 0
0 0 0 1 1 Remainder

(1001010) 2  (1000) 2

1 0 0 1 Quotient
1 0 0 0 1 0 0 1 0 1 0
 1 0 0 0
0 0 0 1 0 1 0
1 0 0 0
0 0 1 0 Remainder
 Divisor

0 Bn–1 Bn–2 B1 B0
n-bit bus
n
Binary down
counter CLOCK
sequence counter
(SC)
n
n n
Add / Sub Shift, add
and subtract
n+1 - bit Adder Cin control logic

Quotient
setting
n Shift

An An–1 An–2 A1 A0 Qn–1 Qn–2 Q1 Q0

Dividend


Q0
Q0
 Start

A 0
B Divisor
Q Dividend
SC n

Shift left
A, Q

A A–B

No (sign bit of A = 0) Yes (sign bit of A = 1)

A < 0?

Q0 0
Q0 1
A A+B

SC SC – 1

No
SC = 0?

Yes Quotient in Q
Remainder in A
End

0 0 0 1 1 Divisor
1 1 1 0 0 1's complement
+ 1 Add 1
1 1 1 0 1 2's complement of divisor
 A register Q register SC

Initially 0 0 0 0 0 1 0 1 0 Dividend 1 0 0

Shift left A, Q 0 0 0 0 1 0 1 0 0
Subtract B 1 1 1 0 1
Set Q0 1 1 1 1 0 First cycle 0 1 1
Restore (A+B) 0 0 0 1 1
0 0 0 0 1 0 1 0 0

Shift left A, Q 0 0 0 1 0 1 0 0 0
Subtract B 1 1 1 0 1
Set Q0 1 1 1 1 1 Second cycle 0 1 0
Restore (A+B) 0 0 0 1 1
0 0 0 1 0 1 0 0 0

Shift left A, Q 0 0 1 0 1 0 0 0 0
Subtract B 1 1 1 0 1
Set Q0 0 0 0 1 0 Third cycle 0 0 1

0 0 0 1

Shift left A, Q 0 0 1 0 0 0 0 1 0
Subtract B 1 1 1 0 1
Set Q0 0 0 0 0 1 Fourth cycle 0 0 0

Note : Subtract B means add B in

Remainder 0 0 1 1
2's complement form

Quotient
 0 0 0 1 1 Divisor
1 1 1 0 0 1's complement
+ 1 Add 1
1 1 1 0 1 2's complement

A Register Q Register
Initially 0 0 0 0 0 1 0 0 0
Left shift A, Q 0 0 0 0 1 0 0 0
Subtract B 1 1 1 0 1
Set Q0 1 1 1 1 0

Restore (A + B) 0 0 0 0 1 0 0 0 0
Left shift A, Q 0 0 0 1 0 0 00
Subtract B 1 1 1 0 1
Set Q0 1 1 1 1 1

Restore (A + B) 0 0 0 1 0 0 0 0 0

Left shift A, Q 0 0 1 0 0 0 0 0
Subtract B 1 1 1 0 1
Set Q0 0 0 0 0 1

0 0 0 1
Left shift A, Q 0 0 0 1 0 0 0 1
Subtract B 1 1 1 0 1
Set Q0 1 1 1 1 1

Restore (A + B) 0 0 0 1 1 0 0 1 0
0 0 0 1 0
Remainder Quotient



 A Register Q Register

0 0 0 0 0 0 1 0 0 0 1 Dividend

Shift 0 0 0 0 0 1 0 0 0 1

Subtract B 1 1 1 1 0 1
1 1 1 1 1 0
First cycle

Restore (A+B) 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 1 0

Shift 0 0 0 0 1 0 0 0 1 0

Subtract B 1 1 1 1 0 1
1 1 1 1 1 1 Second cycle

Restore (A+B) 0 0 0 0 1 1 0 0 1 0 0
0 0 0 0 1 0

Shift 0 0 0 1 0 0 0 1 0 0

Subtract B 1 1 1 1 0 1
0 0 0 0 0 1 Third cycle

0 1 0 0 1

Shift 0 0 0 0 1 0 1 0 0 1

Subtract B 1 1 1 1 0 1
1 1 1 1 1 1 Fourth cycle

Restore (A+B) 0 0 0 0 1 1 1 0 0 1 0
0 0 0 0 1 0

Shift 0 0 0 1 0 1 0 0 1 0

Subtract B 1 1 1 1 0 1
0 0 0 0 1 0 Fifth cycle

Remainder 0 0 1 0 1

Quotient
 A Register Q Register
Initially 0 0 0 0 0 1 1 1 Dividend
Shift 0 0 0 0 1 1 1
Subtract B 1 1 0 1
Set Q0 1 1 0 1 First cycle

Restore (A+B) 0 0 1 1
0 0 0 0 1 1 1 0

Shift 0 0 0 1 1 1 0
Subtract B 1 1 0 1
Set Q0 1 1 1 0 Second cycle

Restore (A+B) 0 0 1 1
0 0 0 1 1 1 0 0

Shift 0 0 1 1 1 0 0
Subtract B 1 1 0 1

0 0 0 0 Third cycle

1 0 0 1

Shift 0 0 0 1 0 0 1
Subtract B 1 1 0 1
Fourth cycle
Set Q0 1 1 1 0

Restore (A+B) 0 0 1 1
0 0 0 1 0 0 1 0

Remainder Quotient
 (0001) 2  1 (0010) 2  2

Q V  R





 1100 2 1011

Exponent
5
111101.1000110 1.11101100110 x 2
Significant digits Scaling factor
 



32 bits
31 30 23 22 0

S E' M

Sign of 8-bit signed 23-bit

number : exponent in mantissa fraction
0 signifies + excess-127
1 signifies – representation
E'–127
Value represented = ± 1.M  2

64 bits
63 62 52 51 0

S E' M

Sign 11-bit 52-bit

excess-1023 mantissa fraction
exponent
E'–1023
Value represented = ± 1.M  2
  





 
1259.125 10

Q R

16 1259 11 B LSD
Fraction Base Product
16 78 14 E 0
0.125 × 2 = 0  25
16 4 4 4 MSD
0
0 0.25 × 2 = 0  50

 (1259) 10 (4EB) 16 1
0.50 × 2 = 1  00
4 E B Hex number

0 1 0 0 1 1 1 0 1 0 1 1 Binary number

 (1259) 10 (100 1110 1011) 2

 (0.125) 10 (0.001) 2

  2 10

 137 10
12


31 30 23 22 0
0 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0

Sign Exponent Mantissa

 1033 10 12

63 62 52 51 0
0 1 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0

Sign Exponent Mantissa

307.1875 10

Q R

16 307 3 LSD

16 19 3

16 1 1 MSD

0
 Fraction Base Product
1 3 3 Hex number
0.1875 × 2 = 0  375 0
0 0 0 1 0 0 1 1 0 0 1 1 Binary number

0
 (307) 10 (133) 16 0.375 × 2 = 0  75

 (307) 10 (1 0 011 0 011) 2 1

0.75 × 2 = 1  50

0.50 × 2 = 1  00

 (0.1875) 10 (0.0011) 2


 28

 E 135 10 10000111 2

31 30 23 22 0
1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

Sign Exponent Mantissa

 E 1031 10 10000000111 2

1 100 0000 0111 0011001100110......0

Sign Exponent Mantissa (52- bits)

 63 62 52 51 0
1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0

Sign Exponent Mantissa

(– 0.75) 10

0.75  2 = 1.50 1
1
0.50  2 = 1.00
 – (0.75)10 = – (0.11)2

– 1.1  2 – 1

 126 10 ( 01111110) 2


31 30 23 22 0
1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sign Exponent Mantissa (23 - bits)

(9 - bit) (8 - bit)

(309.1875)10

31 30 23 22 0
0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 0

63 62 52 51 0
0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 0
 (0.0625)10

31 30 23 22 0
0 0 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0

63 62 52 51 0
0 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0

31 30 23 22 0
a) 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0

31 30 23 22 0
b) 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0

E
E

 
E 

E 

1
 1

m 1  r e1

m 2  r e2 e1  e2

e2  e1
  10 2 10 4  10 2
 10 4

A= 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0

B= 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0

Mantissa of A = 0 0 1 0 0 0 0 0 0
Mantissa of B = 0 0 0 0 0 1 0 0 0
Mantissa of result = 0 0 1 0 0 1 0 0 0

Result (A + B) = 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 = 44920000 H
 Mantissa of A = 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Mantissa of B
+
2's complement of Mantissa of B = 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 1 1's complement of B
0 0 0 1 1 1 0 0 0 1 Add 1
1 1 1 1 1 1 0 0 0 2's complement of B

Result (A – B) = 0 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 = 448E0000H

( 0.5) 10 (0.4375) 10

( 0.5) 10 ( 0.1) 2 1.0  2 – 1

0
0.4375  2 = 0.875
1
0.875  2 = 1.75
1
0.75  2 = 1.50
1
0.50  2 = 1.00

 (0.4375) 10 (0.0111) 2 (1.110) 2  2 – 2

(1.110) 2  2 – 2 0.111  2 – 1

1.0  2 – 1 0.111  2 – 1 1.111  2 – 1

  or – 
 ADD

A Augend
B Addend

N N N Increment
Exponents
A=0 B=0 smaller
equal
exponent
?
Y Y

C=B C=A Y
Shift
mantissa
Add right
signed
mantissa

Mantissa N
=0
Y ?
C=0 Mantissa
=0 Y
?
Return
C = Number having
N greater exponent

Y Mantissa
Increment exponent Return
overflow

N
Shift mantissa
right

Result N
normalized
?
Exponent N Decrement
overflow Y exponent
?
Round
Y result Shift mantissa
Report left
overflow

Exponent N
underflow

Report
underflow

Return
 Subtract

A Minuend
B Subtrahend

Change the
sign of B

N N N Increment
Exponents
A=0 B=0 smaller
equal
exponent
?
Y Y

C=B C=A Y
Shift
mantissa
Add right
signed
mantissa

Mantissa N
=0
Y ?
Mantissa
C=0
=0 Y
?
Return
C = Number having
N greater exponent

Y Mantissa
Increment exponent Return
overflow

N
Shift mantissa
right

Result N
normalized
?
Exponent N Decrement
overflow exponent
Y
?
Round
Y result Shift mantissa
Report left
overflow

Exponent N
underflow

Report
underflow

Return
 EA  E B
MB
EA EB
MA
 EB EA EB EA MB MA

2-way 8-bit Swap

Multiplexer Subtractor

Sign M of number
with smaller E

S : Sign
E : Exponent
M : Mantissa n = |EA – EB| Shifter
M of number
with larger E
n bits
to right
S A SB Add/Sub

Sign
Control Mantissa
unit Add / Sub adder/subtractor

Magnitude
M

Leading zeros
detector

X
Normalizer
E

8-bit
Subtractor

E–X

SR ER MR
1-bit 8-bit 23-bit

32-bit result

EA EA  E B
EB EA  E B
 ( SA and S B

SR

ER
( 075
. ) 10 (– 0.275) 10

1  (0.75) 10 (0.11) 2 1.1  2 – 1

0.75  2 = 1. 5
1
0.5  2 = 1.0

0
0.275  2 = 0.55
1
 – (0.275) 10 – (0.01000110) 2
0.55  2 = 1.10
0 – (1.000110  2 – 2 )
0.1  2 = 0.20
0
0.20  2 = 0.40 – ( 0.1000110  2 – 1 )
0
0.40  2 = 0.80
1
0.80  2 = 1.60
1
0.60  2 = 1.20
0
0.20  2 = 0.40

1.1  2 – 1  (– 0.1000110  2 – 1 ) 0.1111010  2 – 1

0.1111010  2 – 1 1.111010  2 – 2

 
 Multiply

A Multiplicand
B Multiplier

Yes Is
A = 0 or
B=0?

No

Result 0 Add exponent

and subtract bias

Yes
Exponent
overflow
?
Report
No overflow

Exponent Yes
underflow
?
Report
No underflow

Multiply the
mantissas and
determine sign of result

Normalized result

Return
 ( 0.5) 10 (0.4375) 10

( 0.5) 10 1.0  2 – 1
( 0.4375) 10 (1.110) 2  2 – 2

1. 0 0 0
 1. 1 1 0
0 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 1 1 0 0 0 0

1.110000  2 – 3

1.110000  2 – 3

1 2– 3 + 1 2– 4 1 2– 5 (0.21875) 10


 Divide

A Dividend
B Divisor

Yes
A=0? C=0

No

Yes
B=0? C=

No

Subtract exponent
and add bias

Yes Report
Exponent
overflow overflow
?

No

Exponent Yes Report

underflow underflow
?

No

Divide the mantissas and

determine the sign

Normalized the result

Return
 0 1 0 1
 0 0 1 1
1 0 0 0

S3
90  30

C n– 1 S n– 1
Cn
C4 C3
S3
 Ai Pi
Bi Si

Gi
Ci+1

 Ci

Gi
Ai Bi

Pi
Gi Ci + 1 Ci + 1
Cn Carry - lookahead generator

Pn–1 Gn–1 Pn–2 Gn–2 P0 G0

Sn–1 Sn–2 S0

1-bit 1-bit 1-bit

adder adder adder
Cn–1 Cn–2 C1 Cin

An–1 Bn–1 An–2 Bn–2 A0 B0

A B
4 4

Cout 4-bit Cin

C4 Adder
G0
C0 P0
C8
4

C 12 S

C 28

C 32 S 31

S 31 C 32

C 4 C 8 C 12

C4 C8 C 12
 S3 S2 S1 S0

Sum
logic

Cout

Carry
lookahead
C4 generator C3 C2 C1

Cin

P3 G3 P2 G2 P1 G1 P0 G0

PG
logic

A3 B3 A2 B2 A1 B1 A0 B0

G IK PKI

P0I G I0 G 3  P3 G 2  P3 P2 G 1  P3 P2 P 1 G 0

Gi Pi
G IK
PKI

C 16
 x15-12 y15-12 x11-8 y11-8 x7-4 y7-4 x3-0 y3-0

c12 c8 c4
c16 4-bit adder 4-bit adder 4-bit adder 4-bit adder c0

s15-12 s11-8 s7-4 s3-0

I I I I I I I I
G3 P3 G2 P2 G1 P1 G0 P0

Carry-lookahead logic

II II
G0 P0

G I3  P3I G I2  P3I P2I G I1  P3I P2I P1I G I0  P3I P2I P1I P0I C 0

C4

C 4 C 8 C 12 C 16

G IK PKI
G IK PKI
Gi Pi
C0
C 15
C 12 S 15
S 15 C 16
S 15 C 16
S 15

C 32 S 31 C 16 S 15
C 32 S 31
 S 63 C 64

0 1 0 0 0 0 (16)
– 0 0 0 0 1 0 (2)
0 0 1 1 1 0 (14)

24
21
 0 1 0 0 1 1 Multiplicand
 0 +1 0 –1 0 0 Multiplier
0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0
+ 1 1 1 1 1 0 1 1 0 1 2's complement of the multiplicand
+ 0 0 0 0 0 0 0 0 0
+ 0 0 0 1 0 0 1 1
+ 0 0 0 0 0 0 0
0 0 0 0 1 1 1 0 0 1 0 0

Note : Shaded portion indicates sign extensions

 0 1 1 1 0 (+14) Multiplicand
1 1 0 1 1 (–5) Multiplier
0 –1 1 0 –1 Recoded multiplier

0 1 1 1 0 Multiplicand
 0 –1 +1 0 –1 Recoded multiplier
1 1 1 1 1 1 0 0 1 0 2's complement of the multiplicand
+ 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 1 1 1 0
+ 1 1 1 0 0 1 0 2's complement of the multiplicand
+ 0 0 0 0 0 0
1 1 1 0 1 1 1 0 1 0 (–70)

Note : Shaded portion indicates sign extensions

1 0 1 1 0 0 Multiplier
–1 +1 0 –1 0 0 Recoded multiplier

1 1 0 0 1 1 Multiplicand
 –1 +1 0 –1 0 0 Recoded multiplier
0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 1 1 0 1 2's complement of the multiplicand
+ 0 0 0 0 0 0 0 0 0
+ 1 1 1 1 0 0 1 1
+ 0 0 0 1 1 0 1 2's complement of the multiplicand
0 0 0 1 0 0 0 0 0 1 0 0 (260)

Note : Shaded portion indicates sign extensions

 97
 1 0 1 1 1 (–9) Multiplicand
0 1 1 1 0 (7) Multiplier
+1 0 0 –1 Recoded multiplier
Implied
zero

1 0 1 1 1 Multiplicand
 +1 0 0 –1 Recoded multiplier
0 0 0 0 1 0 0 1 2's complement of the multiplicand
0 0 0 0 0 0 0
0 0 0 0 0 0
1 0 1 1 1
1 1 0 0 0 0 0 1 (– 63)

(  34) 10
(1011110) 2 ( 22) 10 ( 0010110) 2

1 0 1 1 1 1 0 Multiplier
–1 +1 0 0 0 –1 0 Recoded multiplier

0 0 1 0 1 1 0 Multiplicand
1 1 0 1 0 1 0 2’s complement of multiplicand

0 0 1 0 1 1 0
 –1 +1 0 0 0 –1 0
0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 1 0 1 0 2’s complement of multiplicand
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0
1 1 0 1 0 1 0 2’s complement of multiplicand
1 1 1 0 1 0 0 0 1 0 1 0 0 Result (–748) in 2's complement form
 ( 21) 10

Multiplicand

Bn–1 Bn–2 B1 B0
n-bit bus
n Binary Down
Counter CLOCK
Sequence Counter
(SC)
n
n
Cin Add / Sub
Shift, add
n-bit Adder and subtract
Enable control logic
Add/subtract
Enable
Shift right
n

An–1 An–2 A1 A0 Qn–1 Qn–2 Q1 Q0 Q–1

Multiplier 1-bit
Register
Initial settings : A 0 and Q–1 = 0

Q 1

Q 1
C in
C in

Q0 Q 1

Q0 Q 1


Q 1

Q0 Q 1 Q0
Q 1

A n 1 A n 2 A n 1
 Flowchart Algorithm
Start

Step 1 : Load A = 0, Q–1 = 0

A 0 Q–1 0 B = Multiplicand
Q = Multiplier
B Multiplicand
SC = n
Q Multiplier
SC n
Step 2 : Check the status of Q0Q–1
if Q0Q–1 = 10 perform A A–B
if Q0Q–1 = 01 perform A A+B
= 10 = 01
Q0, Q–1
Step 3 : Arithmetic shift right : A, Q, Q–1
A A–B = 11 A A+B
= 00 Step 4 : Decrement sequence counter
if not zero, repeat step 2 through 4
Step 5 : Stop

Arithmetic Shift Right: A, Q, Q–1

SC SC – 1

No
SC = 0?

Yes

End

(  7)

Multiplicand (B) = (–7) = 1 0 0 1 , Multiplier (Q)= (3) = 0 0 1 1

A Q
SC Operation
A3 A2 A1 A0 Q3 Q2 Q1 Q0 Q–1

1 0 0 0 0 0 0 0 0 1 1 0 Initial
0 0 0 0 A
0 1 1 1 2’s complement of B Q0 Q–1 = 1 0
+
0 1 1 1 0 0 1 1 0  AA– B

0 1 1 0 0 1 1 1 0 0 1 1 Arithmetic shift right

0 1 0 0 0 0 1 1 1 0 0 1 Arithmetic shift right
0 0 0 1 A Q0 Q–1 = 0 1
+ 1 0 0 1 B
1 0 1 0 1 1 0 0 1  AA+B

0 0 1 1 1 0 1 0 1 1 0 0 Arithmetic shift right

0 0 0 1 1 1 0 1 0 1 1 0 Arithmetic shift right

Result : = 1 1 1 0 1 0 1 1 = – 21
 Sign extension 1 1 1 0 1 0 0 Implied 0 to
right of LSB
0 –1 –2

0 1 1 0 1 1 0 Implied 0 to
right of LSB
+2 –1 –1

1 1 0 1 0 1 Multiplicand
 +2 –1 –1 Bit pair recoded multiplier
0 0 0 0 0 0 0 0 1 0 1 1 2's complement of the multiplicand
+ 0 0 0 0 0 0 1 0 1 1 2's complement of the multiplicand
+ 1 1 1 0 1 0 1 0 Multiplicand × (+2) = 1101010
1 1 1 0 1 1 0 1 0 1 1 1 (–297)

1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0

–1 0 0 +1 0 0 0 –1 +1 –1 0 0 +1 –1 +1 –1

1 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0

–2 +1 0 –1 +1 0 +1 +1
 1 0 1 1 0 0 0

–1 –1 0

0 1 0 1 1 1 Multiplicand
1 0 1 0 0 0 1's complement
+ 1 Add 1
1 0 1 0 0 1 2's complement

0 1 0 1 1 1
 –1 –1 0
0 0 0 0 0 0 0 0 0 0 Multiplicand × 0
+ 1 1 1 0 1 0 0 1 2's complement of the multiplicand
+ 1 0 1 0 0 1 2's complement of the multiplicand
1 0 0 0 1 1 0 1 0 0 (–460)

1 0 1 1 0 0 Multiplier
–1 +1 0 –1 0 0 Recoded multiplier

1 1 0 0 1 1 Multiplicand
 –1 +1 0 –1 0 0 Recoded multiplier
0 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 1 1 0 1 2's complement of the multiplicand
+ 0 0 0 0 0 0 0 0 0
+ 1 1 1 1 0 0 1 1
+ 0 0 0 1 1 0 1 2's complement of the multiplicand
0 0 0 1 0 0 0 0 0 1 0 0 (260)

Note : Shaded portion indicates sign extensions

 1 0 1 1 0 0 0

–1 –1 0

1 1 0 0 1 1 Multiplicand
0 0 1 1 0 0 1's complement
+ 1 Add 1
0 0 1 1 0 1 2's complement

1 1 0 0 1 1
 –1 –1 0
0 0 0 0 0 0 0 0 0 0 0 Multiplicand × 0
+ 0 0 0 0 0 1 1 0 1 2's complement of the multiplicand
+ 0 0 0 1 1 0 1 2's complement of the multiplicand
0 0 1 0 0 0 0 0 1 0 0 (+260)

Sign 1 1 0 1 1 0 0 Implied 0
extension to right of LSB
–1 +2 –2

0 1 1 1 1 Multiplicand
1 0 0 0 0 1's complement
+ 1 Add 1
1 0 0 0 1 2's complement

Multiplicand  (+ 2) = Shift left multiplicand by 1 bit = 011110

Multiplicand  (– 2) = Shift left 2's complement multiplicand by 1 bit = 100010
 0 1 1 1 1 Multiplicand
–1 +2 –2 Multiplier
1 1 1 1 1 0 0 0 1 0 Multiplicand × (–2) = 100010
0 0 0 1 1 1 1 0 Multiplicand × (+2) = 011110
1 1 0 0 0 1 2's complement of multiplicand
1 1 0 1 1 0 1 0 1 0 (–150)

0 0 1 1 0 Implied 0 to
right of LSB
+1 –1

1 1 0 1 1 Multiplicand
0 0 1 0 0 1's complement
1 Add 1
0 0 1 0 1 2's complement

1 1 0 1 1 Multiplicand
+1 –1 Multiplier
0 0 0 0 0 0 0 1 0 1 2's complement of multiplicand
1 1 1 1 1 0 1 1 Multiplicand
1 1 1 1 1 1 0 0 0 1 (–15)

(110110101111001)2

(110110101111001) 2

Sign 1 1 1 0 1 1 0 1 0 1 1 1 1 0 0 1 0 Implied 0
extension to right of LSB
0 –1 –1 +1 +2 0 –2 +1

0 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 Implied 0
to right of LSB
+1 +2 –1 –1 –2 +1 +1 +1
 0 1 1 0 1 1 0 Implied 0 to
right of LSB
+2 –1 –1

1 1 0 1 0 1 Multiplicand
0 0 1 0 1 0 1's complement
+ 1 Add 1
0 0 1 0 1 1 2's complement

1 1 0 1 0 1 Multiplicand
+2 –1 –1 Multiplier
0 0 0 0 0 0 0 0 1 0 1 1 2's complement of multiplicand
0 0 0 0 0 0 1 0 1 1 2's complement of multiplicand
1 1 1 0 1 0 1 0 Multiplicand × (+2) = 1101010
1 1 1 0 1 1 0 1 0 1 1 1 (–297)

(–10  –10  100) 10

0 1 0 1 0 (10)2
1 0 1 0 1 1's complement of (10)2
1 Add 1
1 0 1 1 0 2's complement of (10)2 : (–10)

1 0 1 1 0 Multiplier
–1 +1 0 –1 0 Recoded multiplier
 1 0 1 1 0 Multiplicand (–10)
–1 +1 0 –1 0 Recoded multiplier
0 0 0 0 0 0 0 0 0
+ 0 0 0 0 1 0 1 0 2's complement of multiplicand (+10)
+ 0 0 0 0 0 0 0
+ 1 1 0 1 1 0 Multiplicand (–10)
+ 0 1 0 1 0 2's complement of multiplicand (+10)
0 0 1 1 0 0 1 0 0 Result = (100)

Sign extension 1 1 0 1 1 0 0 Implied 0 to

right of LSB
–1 +2 –2

1 0 1 1 0 Multiplicand (–10)
–1 +2 –2 Bit pair recoded multiplier
0 0 0 0 1 0 1 0 0 Multiplicand × (–2)
1 1 0 1 1 0 0 Multiplicand × (+2)
0 1 0 1 0 2's complement of multiplicand (+10)
0 0 1 1 0 0 1 0 0 Result = (100)

0 0 1 0
01 11
 0 1 1
 1 1 0
0 0 0
+ 0 1 1 0  Shift left
+ 0 1 1 0 0  Shift left
1 0 0 1 0

A1 A0


B1 B0

B0 A1 B0 A0 Partial products
+
B1 A1 B1 A0 P0 = B0A0

P1 = B0A1 + B1A0

P3 P2 P1 P0 P2 = B1A1 + Carryout of P1

P3 = Carryout of P2

2 2

 B1 A 1 B1 A0 B0 A1 B0 A0

Half-adder Half-adder

P3 P3 P1 P0

A3 A2 A1 A0

B3 B2 B1 B0

B0A3 B0A2 B0A1 B0A0 Partial

product

B1A3 B1A2 B1A1 B1A0

B2A3 B2A2 B2A1 B2A0

+ B3A3 B3A2 B3A1 B3A0

P7 P6 P5 P4 P3 P2 P1 P0
B0
A3 A2 A1 A0
B1
A3 A2 A1 A0

Y3 Y2 Y1 Y0 X3 X2 X1 X0

0 Cin 4-bit binary adder

Cout S3 S2 S1 S0

B2
A3 A2 A1 A0

Y3 Y2 Y1 Y0 X3 X2 X1 X0

0 Cin 4-bit binary adder

Cout S3 S2 S1 S0

B3
A3 A2 A1 A0

Y3 Y2 Y1 Y0 X3 X2 X1 X0

0 Cin 4-bit binary adder

Cout S3 S2 S1 S0

P7 P6 P5 P4 P3 P2 P1 P0
 B0A3 B0A2 B0A1 B0A0

B1A3 B1A2 B1A1 B1A0

B2A3 B2A2 B2A1 B2A0

+ B3A3 B3A2 B3A1 B3A0

P7 P6 P5 P4 P3 P2 P1 P0


 B1A3 0 B1A2 B0A3 B1A1 B0A2 B1A0 B0A1 B0A0

4-bit Ripple Adder

FA FA FA FA 0
4 3 2 1

B2A3 B2A2 B2A1 B2A0

FA FA FA FA 0
8 7 6 5

B3A3 B3A2 B3A1 B3A0

FA FA FA FA 0
12 11 10 9

P7 P6 P5 P4 P3 P2 P1 P0


 B1A2 B0A3 B1A1 B0A2 B1A0 B0A1 B0A0

3-bit Ripple Adder 0

FA 0 FA 0 FA

B2A2 B1A3 B2A1 B2A0

FA FA FA

B3A2 B2A3 B3A1 B3A0

FA FA FA
B3A3

FA FA FA 0

P7 P6 P5 P4 P3 P2 P1 P0

1 1 a
b b2 b
1
1
b
 1
b

1 1
f  b
b 1 b

f(x i )
xi 1 xi 
f (x i )

X0
f(X 0 ) 1 X0  b
f (X 0 )  1 X 20

f(X 0 )
X1 X0 
f (X 0 )
(1 / X 0 – b)
X1 X0 
(1 / X 0 ) 2
X1 X 0  (2  b  X 0 )

Xi 1 X i  (2  b  X i )

i  1 2i (b)

X0
      

1
X0
10
1  1  1  20 7  1 13 13
 X1  2  7      
10  10  10  10 10  10 10 100

13  13  13  200 91  13 109 1417

 X2  2  7      
100  100  100  100 100  100 100 10000

14284777
 X3
100000000
 X0
X0
 X1 X 0 (2  X 0 b)
 X2 X 1 (2  X 1 b)
 

1 1
2 2
 
Q0
Q0
 






Program M
counter U
X

4
A A
D D
D D

M
U
X

Data
Address

Register 1
A Address
Instruction Register 2 L
M U Data
U memory
Instruction Register 3
memory X Data
Register file
 Branch

Program M
U Control
counter
X

4
A A
D D ALU
D D operation

M
U
X

Data Mem R
Zero
Address
Register 1
Instruction Register 2 Address
A
Register 3 L
M U Data
Register file U memory
Instruction
memory X Data
Reg W Mem W
 State Combinational logic State
element 1 element 2

Clock cycle

State Combinational logic

element
Program M
counter U
X

4
A
A D
D D
D

Address

Instruction

Instruction
memory
 Write data
ALU operation

Zero
Data

Read register Read data 1

Register
numbers Read register A
Write register L
U
Read data 2
Register file
Reg W
 Mem R

Read data

Address Sign
extend
Data
memory

Data
Mem W
 Branch target address
Program M
counter U
X

PC + 4
4
A
A D
D D
D
PC

Shift left
by
Address 2 bits

Instruction

Instruction
memory

Branch target address

Program M
counter U
X

PC + 4
4
A
A D
D D
D
PC

ALU operation
Shift left by Zero for
2 bits branch logic
Data

Address Read register Read data 1

Sign Register
extend numbers Read register A
Write register L
Instruction U
Read data 2
Register file
Instruction
memory Reg W
 M
U
X
ALU
operation
Zero Mem R
Write data
Read data 1 Read data
Read register 1
A
Address
Instruction Read register 2 L
Read data 2 ALU Data
U
M result memory
Write register U
X Write data
Reg W Mem W

Sign
extend

PC Src

Program M
counter U
X

4
A A
D D
D D

Mem to Reg
Shift left by
2 bits
M
U Mem R
X
ALU
Registers operation
Zero
Write
Read data 4
Read Read data
address
Read data 1
register 1 A
Read Address
Instruction L
register 2 Read ALU Data
U
data 2 M result memory
Instruction Write U
register X Write data
memory
Reg W

ALU Src
Sign Mem W
extend
      

      

  

  

  

  

  

Field 0 rs rt rd shamt funct

Bit positions 31:26 25:21 20:16 15:11 10:6 5:0
(a) R type instruction

Field 35 or 43 rs rt address
Bit positions 31:26 25:21 20:16 15:0
(b) Load or store instruction

Field 4 rs rt address
Bit positions 31:26 25:21 20:16 15:0
(c) Branch instruction
 PC Src

Program M
counter U
X

4
A
A D
D D
D
Mem to Reg
Shift left by
2 bits
M
U Mem R
X

Registers
Zero
Write
Read data Read Read data
address Instruction [25 : 21] Read data 1
register 1 A
Instruction [20 : 16] Read Address
Instruction L
register 2 Read ALU Data
[31:0] U
data 2 M result memory
Instruction M Write U
Instruction X Write data
memory U register Reg W
[15 : 11] X

ALU Src Mem W

RegDst
4 ALU
16 Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5 : 0]
 PC Src

M Branch
Program
counter U
X
Control

4
A
A D
D D
D

Mem to Reg
Shift left by
2 bits
Instruction [31 : 26]
M
U
X Mem R

Registers
Write Zero
Read data Read Read data
address Instruction [25:21] Read data 1
register 1 A
Instruction [20:16] Read Address
Instruction L
register 2 Read ALU Data
[31 : 0] U
data 2 M result memory
Instruction M Write U
Instruction X Write data
memory U register Reg W
[15:11] X
Mem W
ALU Src
RegDst
4 ALU
16 Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5:0]

 

 
 PC Src

Branch
Program M 0
counter U
X
1
Control

4
A
A D
D D
D

Mem to Reg
Shift left by
2 bits
Instruction [31:26]
M 1
U
X Mem R
0

Registers
Zero
Write
Read data
address Read
Instruction [25:21] Read data
Read data 1
register 1 A
Instruction [20:16] Read Address
Instruction L
register 2 Read U ALU Data
[31:0]
data 2 0 M result memory
Instruction M Write U
Instruction X Write data
memory U register
[15:11] Reg W 1
X
Mem W
ALU Src
RegDst
4 ALU
16 Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5:0]
 PC Src

M 0 Branch
Program
counter U
X 1
Control

4
A
A D
D D
D

Mem to Reg
Shift left by
2 bits
Instruction [31:26]
M 1
U
X Mem R
0

Registers Zero
Write
Read data Read Read data
address Instruction [25:21] Read data 1
register 1 A
Instruction [20:16] Read Address
Instruction L
register 2 Read ALU Data
[31:0] U
data 2 0 M result memory
Instruction M Write U
Instruction X Write data
memory U register Reg W
[15:11] 1
X
Mem W
ALU Src
RegDst

16 4 ALU
Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5:0]
 PC Src

Branch
Program M 0
counter U
X
1
Control

4
A
A D
D D
D

Mem to Reg
Shift left by
2 bits
Instruction [31:26]
M 1
U
X Mem R
0

Registers
Zero
Write
Read data
address Read
Instruction [25:21] Read data
Read data 1
register 1
Instruction [20:16] A Address
Instruction Read L
register 2 Read ALU Data
[31:0] U
data 2 0 M result memory
Instruction 0 U
M Write Write data
memory Instruction U register X
[15:11] Reg W 1
1 X
Mem W
ALU Src
RegDst
4 ALU
16 Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5:0]
 Field
000010 address
Bit positions 31:26 25:0

00 2

00 two
 PC Src

0
M M 1 Jump
Jump address [31-0] Branch
U U
X X
1 0
Program
counter 28 PC+4 [31-28] Control

A
D
Shift left by A D
2 bits D
D
26 Mem to Reg
Shift left by
4 2 bits
M 1
Instruction [31:26] U
X Mem R
Instruction [25:0] 0

Registers
Zero
Write
Read data
address Read
Instruction [25:21] Read data
Read data 1
register 1 A
Instruction [20:16] Read Address
Instruction L
register 2 Read U ALU Data
[31:0]
data 2 0 M result memory
Instruction 0 U
M Write Write data
memory Instruction U register X
[15:11] Reg W 1
1 X
Mem W
ALU Src
RegDst
4 ALU
16 Sign 32 ALU operation
Instruction [15:0] extend control

ALUOp
Instruction [5:0]
 Control step
CLK
counter

External
Fixed inputs
I
logic
R
circuit
Condition
codes

Control signals

Control step Reset

CLK
counter
Fixed logic circuit

Step decoder

T1 T2 Tn

in1 External
in2 inputs
I Instruction
Encoder
R decoder
inn
Condition
codes

END

Control signals

28
 

External
inputs
I Sequencer
R (starting and branch address generator)
Condition
codes

Control Address Register (PC) CLK

Address

Control
Read command Memory

Control Word (CW)

Micro instruction register

Decoder

Control signals Control signals to

within CPU system bus

 Clock
cycle 1 2 3 4 5 6 7 8

Instruction

I1 F1 D1 E1 S1

I2 F2 D2 E2 S2

I3 F3 D3 E3 S3

I4 F4 D4 E4 S4
 Interstage buffers

D
F E S
Decode instruction
Fetch Execution Store
and fetch
instruction operation result
operands
B1 B2 B3

Time

1 2 3 4 5 6 7 8 9 10 11 12 13

Instruction 1 FI DI CO FO EI WO

Instruction 2 FI DI CO FO EI WO

Instruction 3 FI DI CO FO EI WO

Instruction 4 FI DI CO FO EI WO

Instruction 5 FI DI CO FO EI WO

Instruction 6 FI DI CO FO EI WO

Instruction 7 FI DI CO FO EI WO

Instruction 8 FI DI CO FO EI WO

Total time required

 B1

Clock
cycle 1 2 3 4 5 6 7 8 9 Time

Instruction

I1 F1 D1 E1 S1

I2 F2 D2 E2 S2

I3 F3 D3 E3 S3

I4 F4 D4 E4 S4

I5 F5 D5 E5
 I1 I2

I1
I2 I2
 
 

I2 IK
I3 I2

I3 IK

Time
Clock cycle 1 2 3 4 5 6
Instruction
I1 F1 E1

I2(Branch) F2 E2
Execution unit idle

I3 F3 X

Ik+ Fk Ek

Ik+1 Fk+1 Ek+1

 T(1)
T(m)

m

 max  i m
1
d
i
 m

m

1


 


th
L : Latch Si : The i stage C : Clock

L L L L L

Input S1 S2 Sk Output

C
Space
i th th
T : The j subtask in the i task
j

1 2 3 4 5
S4 T T T T T
4 4 4 4 4

1 2 3 4 5
S3 T T T T T
3 3 3 3 3

1 2 3 4 5
S2 T T T T T
2 2 2 2 2

1 2 3 4 5
S1 T T T T T
1 1 1 1 1

0 1 2 3 4 5 6 7 8 9 10 Time
(cycles)

T1 n m nm
Tm [ m  ( n  1)]  m  ( n  1)

4 5 20
4  (5  1) 8

Sk   

Sm nm n

m m  ( n  1) m  ( n  1)
 2 .5
4



Hm

n
[ m  ( n  1)] 
Em n
 [ m  ( n  1)]

Hm  Em 

Em

1 1
 ( t / m  d)

f 1
c  mh ( t / m  d) ( c  mh)
 Performance
cost ratio
Peak

t.c
d. h
k
ko
 Control unit

Data Data
R1 C1 R2 C2 Rm Cm
in out

Stage S1 Stage S2 Stage Sm

 S2

S1 

S2 


S2
Ii Ai
External address

Microprogram counter
(PC)

Control memory
Branch (CM)
address

Stage S1

Microinstruction
register IR

Next
External address Decoders
conditions logic

Stage S2

Control signals
 S2 I i 1 A i 1
S1 Ii S2
I i 1
S1 
S1 

S1 S4

S1
S2
S3
S4
Main memory
instruction
Main memory
data

I - cache D - cache

Fetch PC Data read Data write

logic ALU logic
and
decode
logic IR

Register file
(RF)

S1 : IF S2 : OL S3 : EX S4 : OS
(Instruction fetch) (Operand load) (ALU operand) (Operand store)
 S2 S 3 S4

IF/ID ID/EX EX/MEM MEM/WB

1
M
Program
U
counter
X 0 A
D
D
4 Shift left by
A Register 2 bit
D
Write
D
data
Read
data 1 Zero
Read
A Read data
register 1 0
Address L M
Read
U Address U
Read data 2 0 M
Instruction register 2 U ALU Data 1 X
1 X result memory
Write
register Write
Instruction data
memory 16 32
Sign
extend
 Pc Src
IF/ID ID/EX EX/MEM MEM/WB
1
M
Program
U
counter
X 0
A
D
D
Shift by Branch
4 2 bit
A Reg W
D
D Register
Write
data Read
data 1
Read Zero Mem to Reg
Mem R
ALUsrc A
register 1 L Read 1
Address M
Read U data
ALU U
Instruction Read data 2 0 M Address X
U result 0
register 2 Data
1 X memory
Write
register
Reg W Write
Instruction data
memory Instruction
[15:0] Mem W
Signed
16 extend 32
ALU
control
Instruction
[20:16] ALUOp
Instruction 0M
U
[15:11]
1X
RegDst

WB

Instruction
Control M WB
...
... ... ...
EX ... M ... WB ...
... ...

IF/ID ID/EX EX/MEM MEM/WB

 ID/EX
Pc Src
WB EX/MEM
1
Program M Control M WB MEM/WB
U
counter X
0 IF/ID EX M WB

Add
4 Reg W A result Branch
A D
D Shift by D
D Register 2 bit
Write
data
Zero
Read
Read data 1
Address register 1 A Mem R
L
Instruction Read ALU src Address Mem to Reg
U
Read data 2 0 Read
M 1
register 2 data M
U Data U
X X
Write 1 memory 0
register Write
Instruction Reg W
data
memory Instruction
[15:0] Mem W
Signed ALU
16 32
extend control
ALUOp
Instruction
[20:16]
0 M
Instruction
[15:11] U
1 X RegDst
 Source 1

Source 2

Source Source
Register register 1 register 2
file

MUX 1 MUX 2

ALU

Result
register

Destination
(a) Data path
Interstage buffers

Source Result
register register

S
E
store
Execute
result in
(ALU)
register file
B1 B2
Forwarding path
(b) Forwarding path in the processor pipeline
 ID/EX
WB EX/MEM
Control M WB MEM/WB
EX M WB
IF/ID

M
u
Instruction

x
Registers ALU M
u
Program Instruction Data x
M
counter memory memory
u
x
Rs
IF/[Link]
Rt
IF/[Link]
Rt M EX/[Link]
IF/[Link]
Rd u
IF/[Link]
x
Forwarding MEM/WB RegisterRd
unit
R1 R2 R3 R4

R 4  [ R 2 ]  [ R 4 ]  Carry
 Instruction fetch unit

F : Fetch
instruction

Instruction
queue . D:
. E: S:
Dispatch/
. Execute Store
Decode
instruction results
unit

Time
Clock cycle 1 2 3 4 5 6 7 8 9 10
Queue length 1 1 1 1 2 3 2 1 1 1

I1 F2 D1 E1 E1 E1 S1

I2 F2 D2 E2 S2

I3 F3 D3 E3 S3

I4 F4 D4 E4 S4

I5 F5 D5

I6 F6 X

Ik Fx Dk Ek Sk
 I1

I5 I6
I5 I K I6
I4

I6
I1 I2
I 3 I4 IK
Ib+k–1 Ib+k–2 Ib+3 Ib+2 Ib+1 Ib


clock cycle Instruction flow

(a) k-stage pipeline

Branch taken

Ib+k–1 Ib+k–2 Ib -

A delay slot (d) of length k–1

Branch
target
It+2 It+1 It

New instruction flow

Ib : Branch taken
(b) An instruction stream when branch is taken It : Branch target
k : Number of pipeline stages
d : Delay slot

Branch Branch Branch

instruction prediction target
address statistic address
N T
NN NT
T : Branch taken
N : Branch not taken
NN : Last two branches not taken
T
NT : Not branch taken and previous taken
N T TT : Last two branches taken
TN : Last branch taken and previously not taken
N

TN TT
N T
r1 r2 r2 r1 r1

r 3 r1 r3 r1









 Decode Execute Cycle

I1 I2 1
I3 I4 I1 I2 2
I3 I4 I1 3
I4 I3 4
I5 I6 I4 5
I6 I5 6
I6 7
8
 Decode Execute Cycle

I1 I2 1
I3 I4 I1 I2 2
I4 I1 I3 3

I5 I6 I4 4
I6 I5 5
I6 6
7

Decode Window Execute Cycle

I1 I2 1
I3 I4 I1,I2 I1 I2 2
I5 I6 I3,I4 I1 I3 3
I4,I5, I6 I6 I4 4

I5 I5 5
6
 

 

 

 
 New address
Wait Wait

Instruction Instruction Result

Fetch Execute

Discard
 Storage cells
Address Address
0 0
1 1
2 1 0 0 0 1000 2 1 0 0 0 Reading data
Writing data
3 3
4 4
5 5
6 6
n–1 n–1
n n

(a) Write operation (b) Read operation

 Classification of memory

Based on
principle of operation
Read only memory (ROM) Read/write memory (RAM)

Masked PROM EPROM EEPROM Static Dynamic

ROM RAM RAM
Based on physical
characteristics
Erasable Non erasable Volatile Nonvolatile

Based on
mode of access
Sequential Random

Based on
terminology
used for
fabrication
Bipolar MOS
 Secondary storage
devices

Sequential access Random access

devices devices

Magnetic tape
Magnetic Magneto
Optical disk
disk optical disk

Write Once
Floppy Hard Zip CD-ROM Read Many
disk disk disk read-only (WORM) disk
Increasing CPU Increasing Increasing
size speed cost per bit
Primary
cache

Secondary
cache

Main
memory

Magnetic disk, magnetic

tape secondary
memory
 Cache
CPU memory

Main
memory

I/O
processor

Magnetic Magnetic
tapes disks

Auxiliary memory

I : Instruction flow
D : Data flow

I I
Main Secondary
CPU memory memory
D D

M1 M2

(a) Two - level

I
I I - cache I
Main Secondary
CPU memory memory
D D
D D - cache

M2 M3
M1
(b) Three - level

I I I I
Level 1 Level 2 Main Secondary
CPU memory memory
cache cache
D D D D
M1
M2 M3
M4
(c) Four - level
 b b'

T1 T2
X Y

T1
T2
Word line

Bit lines

T1 T2 T1 T2

b b

b

b
 VDD
b b'

T3 T4
T1 T2

(T 3 , T5 ) X Y
(T4 , T6 )
T5 T6

T1
Word line
T2
Bit lines

T1 T2
T1 T2
T1 T2

T1 T2 .
T3
T6 T4 T5
T3 T6 T4 T5

b

Sense line

Storage
capacitor

Control
line
Bit line VCC

Word line

Open : Data stored (logic 1)

T P Close : Data stored (logic 0)
E2

VDD

Address select line

MOSFET
switch
Data line

Fuse
 Output bit
 Quartz window
Ultraviolet light
 ( 200 A
25 V

n-data lines

k-address
lines Memory
unit
k
Read 2 word
n-bit per word
Write

2k 2 10

16  8  128 bits

2 11

2 18  262144
  

D0
D1

D7 D4 D3 D0
I/O3 I/O0 I/O3 I/O0
A0 A0
A9 1K4 A9 1K4

CS WR RD CS WR RD

Chip select

Write

Read

 
 A0
A11

D0
D7

A11 A0 D7 D0 A11 A0 D7 D0 A11 A0 D7 D0 A11 A0 D7 D0

4K8 4K8 4K8 4K8
CS WR RD CS WR RD CS WR RD CS WR RD

RD

WR

A12 0
24 1
Decoder
2
A13
3

Memory cell 8191

Memory cell 8064

63
Data in
62
Line decoder

61

Data
2
6 to 64

out
1

Memory cell 127 Memory cell 0

127 126 125 124 2 1 0

7 to 128 Line decoder

A6 A5 A4 A2 A1 A0
 64  128  8192


b7 b'7 b1 b'1 b0 b'0

W0

FF FF
W1
A0

A1
Address Memory
decoder cells
A2

A3

W15

R/W
Sense/write Sense/write Sense/write
circuit circuit circuit
CS

Data input/output lines: b7 b1 b0

 Word line

ON 0
1
Tunnel Control gate
oxide
Floating gate
Bit line
Source Drain
n+ n+

p - substrate
 SRAM DRAM

Processor Cache Main

memory

Cache
controller

Cache memory system

Number of hits
 100 %
Total number of bus cycles
 1400
 100
1400  100
 
Total wait states 300
Number of memory bus cycles 1500

Cache
M1
Main
CPU memory
Cache Block M2
access replacement

Main-memory
access

System bus
M1

M2
M2 M1
 Cache
M1

Cache Block
access replacement

Main Main
Cache memory
CPU memory
controller M2
controller

Main
memory
access

System bus
 Main Main
memory memory
address

Cache tag memory Cache data memory

1001001111 39 11 10 01 00

1001001110 D4
1001001101 67
1001 0011 39 D4 67 2C
1001001100 2C
1001001011 C3
1001 0001 B2 5A 00 40
1001001010 9A
1001001001 35
1001001000 1A
1001000111 B2
1001000110 5A
1001000101 00 Data
Tag selector
1001000100 40 comparator

Data
5A
OUT
Address in
1001 0001 10
 Main Main
memory memory
address

Cache tag memory Cache data memory

1001001111 39 11 10 01 00

1001001110 D4
1001001101 67
1001 0011 39 D4 67 2C
1001001100 2C
1001001011 C3
1001 0001 B2 E6 00 40
1001001010 9A
1001001001 35
1001001000 1A
1001000111 B2
1001000110 5A
1001000101 00 Data
Tag selector
1001000100 40 comparator

Data
IN E6
Address in
1001 0001 10
 Block 0
Block 1

Block 0

27
 Main memory
Block 0
Block 1
12 bits Cache
memory
Tag
Block 0  
Tag
Block 1 Block i

   
Tag Block 127
Block j

Tag
12
Word
4
 
Main memory address Block 4095
 Main memory
Block 0
Block 1
Block belongs
to set 0 Page 0
  Tag 0

Block 63
Block 64
Block 65
Cache memory Cache memory
Set 0 Tag Tag Page 1

Set 1 Tag
Block 0
Tag
Block 0
  Tag 1
Block 1 Block 1
Block 127
   
Set 62 Tag Tag Block 62  
Set 63 Tag Tag
Block 63 Block 63 Block 4032
Block 4033
Tag Set Word
Page 63

Block belongs
6 6 4
  Tag 63

to set 63
Block 4095
 24

( 2 8  256)

TAG BLOCK WORD

Main memory address = 4 8 4

 2 12

TAG WORD

Main memory address = 12 4

27  128

TAG SET WORD

Main memory address = 5 7 4

  
 

Cache size 1K
Words in each block 4

Tag Block Word

Main memory address = 6 8 2


 

2048
4
512
2

Tag Set Word

Main memory address = 7 8 2

17 bits

log 2 128
Cache size 1K
Words in each block 128

 log 2 8

log 2 64 K log 2 2 16


TAG BLOCK WORD

Main memory address = 6 3 7

16 - bits
2 12

2 10

2 10 2 10  147
 Other bus Other bus
master master Cache
Main
memory

80386 82385 Shared 80386 Cache

memory

Other bus
master

Non-cacheable
80386 Decode
Main
memory Cacheable
Decode

 Reads
 
Program

 Writes 
 Program  Write miss rate  Write miss penalty 
 

Memory accesses
 Miss rate  Miss penalty
Program

Instructions Misses
  Miss penalty
Program Instruction
 CPU time with stalls I  CPI stall  clock cycle
CPU time with perfect cache I  CPI perfect  clock cycle

CPI stall 5.44

CPI perfect 2
5.44
2
 


Address space

Page 0 1 K words

Page 1

Page 2

Page 3 Memory space

Page 4 Block 0 1 K words

Page 5 Block 1

Page 6 Block 2

Page 7 Block 3

13 12
8K=2 4K=2

Words in address space

Words per page
 4 G words
4 K words
Words in memory space 16 M words
Words per page (block) 4 K words

2 24

2 16

Page number Line number

100 0 1 1 1 0 1 0 1 1 0 Virtual address

Table Presence bit

address
000 0 Main memory

001 10 1 Block 0

010 00 1 01 0111010110 Block 1

011 0 Main memory Block 2

address register
100 01 1 Block 3

101 0

110 11 1 MBR

111 0

01 1

Memory page table

 Page 0

Page 1

Page 2

Page 3
Block 0
Page 4
Block 1
Page 5
Block 2
Page 6
Block 3
Page 7
Memory space
12
Address space M=4K=2
13
N=8K=2
 Initial 4 2 0 1 2 6 1 4 0 1 0 2 3 5 7

Least 4 4 4 4 4 0 0 2 6 6 6 4 1 0 2
recently 2 2 2 0 1 2 6 1 4 4 1 0 2 3
used
0 0 1 2 6 1 4 0 1 0 2 3 5
1 2 6 1 4 0 1 0 2 3 5 7

Initial 4 2 0 1 2 6 1 4 0 1 0 2 3 5 7

4 4 4 4 4 2 2 0 0 0 0 1 6 4 2
2 2 2 2 0 0 1 1 1 1 6 4 2 3
0 0 0 1 1 6 6 6 6 4 2 3 5
1 1 6 6 4 4 4 4 2 3 5 7
 Logical address

Segment Page Word

Segment table Page table

Block Word

Physical address

2K
2K
 Physical
memory
Linear address Translation lookaside HIT
buffer (TLB)

Segment Page MISS

Block

Segment table Page table

+
Block Word

(a) Associative memory (TLB) (b) Working of TLB

 Logical address

7-bits 5-bits 12-bits

Segment Page Word

Segment table Page table

127 31
30

1 1
0 0

Block Word

12-bits 12-bits

Physical address
 Local bus Main
Processor Cache memory

Local I/O
controller

System bus

Expansion
Network SCSI Modem Serial
bus interface

Expansion bus

Local bus Main

Processor Cache memory

Local I/O
controller

System bus

SCSI P 1394 Graphics Video LAN

High speed bus

Expansion
FAX Modem Serial
bus interface

Expansion bus
 1 0 1 0 1 0
Logical 1 (+5 V)
Crystal
Logical 0 (0 V)
oscillator

t0
t0  t1
t1
t2

Bus clock

Address
bus

Data bus

RD

t0 t1 t2
Bus cycle

t1
t2

t1
 Bus clock

Address
bus

Data bus

WR

t0 t1 t2
Bus cycle

Bus clock

Signals seen by master tAM

Address

tDM

Signals seen by slave tAS

Address

Data
tDS
t0 t1 t2 Time

t0

t AM
 t1
t DS
t DM t2 t 2  t DM

t2

t2 – t0

1 2 3 4

Clock

Address

Data

Slave-ready

RD
 Address bus

RD

Master-ready / Ready

Slave-ready / Accept

Data bus

t0 t1 t2 t3 t4 t5
Bus cycle
 Address bus

Data bus

WR

Master-ready / Ready

Slave-ready / Accept
t0 t1 t2 t3 t4 t5
Bus cycle

Data bus
Source Destination
unit Strobe unit

(a) Block diagram

Valid data
Data

Strobe

(b) Timing diagram

 Data bus
Source Destination
unit Strobe unit

(a) Block diagram

Valid data

Strobe

(b) Timing diagram

 Data bus
Source Data valid Destination
unit unit
Data accepted

(a) Block diagram

Data bus Valid data

Data valid

Data accepted

(b) Timing diagram

Source unit

Place data on
1.
the bus
Destination unit

2. Enable data Accept data from

valid signal 3. the bus

Disable data 4. Enable data

5.
valid signal accepted signal

6. Invalidate data 7. Disable data

on the bus accepted signal

Ready to accept data

Initial State

(c) Sequence of events

 Data bus
Source Data valid Destination
unit Ready for data unit

(a) Block diagram

Ready for data

Data valid

Data bus Valid data

(b) Timing diagram

Source unit Destination unit

1. Ready to accept data

Enable ready for data signal
2.
Place data on bus
Enable data valid

Accept data from bus

3.
Disable ready for data signal

Disable data valid

4. Invalidate data on bus

Initial state (c) Sequence of events

 Master 1 Master 2 Master N

Bus access Bus access Bus access

logic logic logic

Bus grant
Bus request
Controller
Bus busy
 Master 1 Master 2 Master N

Bus access Bus access Bus access

Module logic logic logic
address

Controller
Bus request
Bus busy
 Master 1 Master 2 Master N

Bus access Bus access Bus access

logic logic logic

Bus grant 1
Bus request 1
Bus grant 2
Bus request 2
Controller
Bus grant N
Bus request N
Bus busy


 VCC

ARB0

ARB1

ARB2

ARB3

Start Arbitration

1 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0

0 0 0 1 0 1 1 1 0 1 1 0 0 1 1 1

Interface circuit Interface circuit Interface circuit

device A device B device N

Fig. 4.7.4 A distributed arbitration scheme

 Memory
address
space Total
address
space

I/O
address space
 Memory Total
address address
space space I/O
address
space

(a) Memory space (b) I/O space

 Start I/O
routine

Get I/O port A

status register

Is
Yes Call the I/O port A
service request
bit set service routine
?

No

Get I/O port B

status register

Is
Yes Call the I/O port B
service request
bit set service routine
?

No

Get I/O port C

status register

Is
Yes Call the I/O port C
service request
bit set service routine
?

No

End
 Interrupt request
I/O
CPU system
Interrupt acknowledgment
 Assert interrupt
request line

Complete current
instruction
Interrupt
Main Program
service
routine

PC
Put current program

sh
Pu
counter value on stack

Load program counter

Po
with address of

p
PC
interrupt service routine RET

Execute interrupt
service routine

Execute return from

the interrupt

Continue where
interrupted

it
 INTR

Processor
Device Device Device
1 2 n
INTA

INTR
 INTR

INTR1

INTA1 Device Device

1 2

INTRn

INTAn Device Device

Processor 1 2

Priority arbitration
circuit
 Start

Initialize counter
Initialize source pointer

Initialize port address

Get byte

Send byte

No
Last byte ?

Yes

Stop
 CPU DMA
Start

Request I/O transfer Acknowledge

Send addresses of
source and destination Request bus
and number of bytes
to transfer

No
Bus free !

Yes

Perform other activities Activate address lines

Perform data transfer

Release bus

Total data
bytes No
transferred

Yes

Notify CPU of
Acknowledge
completion

Stop
 Data bus

Address bus

Control bus

RD WR RS DS DMA REQ
Data Data Address Control
counter register register I/O devices
logic
BG BR INTR DMA ACK

DMA
HLDA HOLD
NTR

Processor
EOP
 Start Start Start

Is
Is Is
I/O device No
I/O device No I/O device No ready for
ready for ready for
data transfer
data transfer data transfer
?
? ?
Yes
Yes Yes
DMA acquires
DMA acquires DMA acquires the control of
the control of the control of buses from processor
buses from processor buses from processor

Transfers one byte

Transfers one Transfers one
byte byte
Is
No terminal
DMA relinquishes count exhausted
control of buses to Is ?
terminal Is
processor No
count Yes I/O device Yes
exhausted ready for
? data transfer
Is ?
Is No I/O device
Yes No
terminal ready for
No data transfer
count
exhausted ? DMA relinquishes
control of buses to DMA relinquishes
? control of buses to
Yes processor
processor
Yes

Stop Stop Stop

(a) Single transfer (b) Block transfer (c) Demand transfer

 Processor Main memory

System bus

Disk DMA Keyboard

Printer
controller controller

Disk Disk Network

interface

Memory

Address

Bus Data

Control

HOLD DRQ Floppy Data

Disk Floppy Disk
Processor HLDA DMA DACK Controller Control Drive (FDD)
(FDC) status

Interrupt request

Interrupt request
DACK

EOP
 TX TX
DTE RX RX DCE
(Transmitter) (Receiver)
GND GND
 USB Cable
USB USB
Host Device(s)

Front view

Front view
2 1

1 2 3 4
3 4

(a) (b)
 1 1 0 0 1 1 0 1 0 0 1 0 0
Digital data

NRZI data

Digital data

NRZI data
1 2 3 4 5 6

Stuffed bit
 Start

Data absent
dle

Data present (Send data)

Clear count

Get bit

Bit = 0 Bit Bit = 1

status ?

nvert output

1
Output

0 Count = Count + 1

Is No
count = 6
?

Yes

Send sync
bit

Clear count

No
Transmission
over ?

Yes
 

8 bits 1 to 1023 Bytes 16 bits

PID Data CRC 16

(a) Data packet

8 bits 7 bits 4 bits 5 bits

PID ADDR ENDP CRC 5

(b) Token packet

8 bits
PID

(c)Handshaking packet

8 bits 11 bits 5 bits

PID Frame number CRC5

(d) Start of frame packet

X5  X 2  1
X 16  X 15  X 2  1
 Direction of 0 1 0 1 1 1 0
magnetization

One-bit
 Spindle
Sector

Read/write Direction of
head Arm Motion

Moving Arm

Rotating Shaft

Read/write Head (1 per surface)

Surface 7

Surface 6

Surface 5

Surface 4

Surface 3 Direction of
Arm Motion

Surface 2

Surface 1

Surface 0

Magnetizing
Magnetic
current
yoke

Air
gap
Magnetic
thin film
 Sectors Tracks
Inter-track Gaps
Inter-sector Gap
S6

S6
SN
S5

SN
S5

S1
S4
S4

S1

S2
S3

S3 S2
Index

Physical Sector 0 Physical Sector 1 Physical Sector 29

Sector

ID DATA ID DATA Gap Gap ID DATA

Gap Gap Gap Gap Gap Gap Gap
Field Field Field Field 3 1 Field Field
1 2 3 1 2 2 3
0 0 1 1 29 29
Bytes 17 7 41 515 20 17 7 41 515 20 17 7 41 515 20
600 Bytes/Sector

Synch Track Head Sector Synch

Byte # CRC
# # Byte Data CRC

Bytes 1 2 1 1 2 1 512 2

Fig. 4.10.5 Winchester disk track format (Seagate St506)

Processor
Disk drive
1

Disk
controller

Main Disk drive

memory 2

System bus
  10 6

 10 6
2 2
D  D 
  O    I 
 2   2 
  10 6
 107
 

103 . 67  107
6000

Data transfer rate Average bit density

 Rotation speed
in bytes / sec along a track

172 . 78 K 3600

8 60

Manufacturer's User's Lable for

Lable identification purpose

Write protect knotch

Drive spindle
hole
in disk
8"

Index hole
Drive access
opening in jacket

Aperture in the jacket through which read/write

head makes direct contact with the disk surface

8"
 ONE TRACK

~
~
INDEX POST
SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR SECTOR
PREAMBLE ADDRESS INDEX POSTAMBLE
1 2 3 4 24 25 26
MARK GAP

~
~
INDEX 46 1 33 188
HOLE BYTE
BYTES BYTES BYTES

ID ADDRESS TRACK/SECTOR DATA ADDRESS NEXT ID

MARK ID ID GAP MARK DATA ADDRESS MARK
1 17 1 33
BYTE BYTES BYTE BYTES

TRACK SECTOR
0 0 CHECKSUM DATA CHECKSUM
NUMBER NUMBER

6 BYTES 128 BYTES 2 BYTES

Fig. 4.10.8 IBM 3740 floppy disk sectored track format

3 12 5 14
 strip 0 strip 1 strip 2 strip 3
strip 4 strip 5 strip 6 strip 7
strip 8 strip 9 strip 10 strip 11
strip 12 strip 13 strip 14 strip 15

strip 0 strip 1 strip 2 strip 3 strip 0 strip 1 strip 2 strip 3

strip 4 strip 5 strip 6 strip 7 strip 4 strip 5 strip 6 strip 7
strip 8 strip 9 strip 10 strip 11 strip 8 strip 9 strip 10 strip 11
strip 12 strip 13 strip 14 strip 15 strip 12 strip 13 strip 14 strip 15
b0 b1 b2 b3 f0(b) f1(b) f2(b)

b0 b1 b2 b3 P(b)

block 0 block 1 block 2 block 3 P(0–3)

block 4 block 5 block 6 block 7 P(4–7)
block 8 block 9 block 10 block 11 P(8–11)
block 12 block 13 block 14 block 15 P(12–15)
 block 0 block 1 block 2 block 3 P(0–3)
block 4 block 5 block 6 P(4–7) block 7
block 8 block 9 P(8–11) block 10 block 11
block 12 P(12–15) block 13 block 14 block 15
P(16–19) block 16 block 17 block 18 block 19

Read/write
head

Magnetic field
Plastic tape
Tape motion
 Parity bit

9 1 1
8 0 1
7 1 0
6 1 0
Tracks Transverse
5 1 0 Direction
4 0 1
3 1 1
2 0 0
1 1 0

File File
File mark
mark

9
bits

File gap Record Record Record Record

gap gap

Number of tracks
 
8
 10 3  
d  Tape length in inches
Tape speed

75 Mbytes / sec  (450  12)

50 in / sec

BL
BL  G L

Block storage capacity 6  10 3

Storage density 3000

2
2  0 .5

10 Mbits / sec 1

200 in / sec 8
Block storage capacity 32 kbytes
Storage density 6. 25 kbytes / in

Tape length
BL  G L

2400  12
5 . 12  0 . 3




tD  d
t D  t G  t SS
 1.6 m

~0.5 m

Disc Rotation

PIT

3T~11T
(0.833~3.054) m

Focused Laser
beam ~ 2 m

Laser beam generator

Lens

Laser beam
or

Output
irr

Photo
M

diode signal

Lens

Lens

Compact disc
Track 7, Sector 2
Track 0, Sector 0
60 Min 03 Sec 74 Sector
00 Min 00 Sec Sector

01 Min 23 Sec 62 Sector

m
m

m

120 mm

117 mm

116 mm

50 mm
Protective Lead IN
layer 46 mm
1.2 mm Lead OUT
15 mm

33 mm
Transparent Information
disc substrate (PIT)
(N = 1.55) Laser beam

Clamping area
 SECTOR

FF
MODE

LAYERED
SEC
MIN

00 X 00 DATA
ECC
10

12 Bytes 4 Bytes 2048 Bytes 288 Bytes

SYNC HEADER DATA L. ECC
 




Keyboard

Interrupt signal
Keyboard Keyboard
Scan code CPU
controller buffer
Trackpad
 Hat switch
Autofire switch
Extra buttons
Trigger
Stick

Base
Extra buttons
Throttle

Suction cup

y
A/D

Computer
x
A/D
Control button

Amplifier

Photoelectric cell

Lens
 Deflection system

Drum with Laser beam Light source

photo mounted

Light detector
 Side view Front view

Phosphor dot

Evacuated tube

Neck
Electron gun

Electron
beam

Fluorescent coating

OFF
ON
Electron
guns
Selection
B of shadow mask
G
R

Red
Magnified
Blue phosphor-dot
Green triangle

Screen
 

    

 
Ribbon
Signal synchronized hammers
Paper

Print cylinder
 Dot matrix printhead

Solenoid
Paper
Print wires

Ribbon
97

Print wires

(a) Dot pattern for A (b) Dot pattern for A

 

Sprayed ink
forms character

r
Pape

ics
raph
p u ter G
Com By e
. P. Gods
A

Drum

Nozzel Ink fountain

Horizontal Vertical
places plates

Electrical charged
plate control direction
of ink jet spray
 

Piezo disk
(Piezo electric)
Charge
Heating Paper
resistor

Ink droplet

Print head
nozzle Ink droplet
Paper

(a) Bubble-jet method (b) Piezo electric method

 Paper exit

Mirror

Laser
Toner
scanning unit
coated roller

Toner Charging
hopper electrode

Photoconductive
drum

Fuser

Paper Tray

  


8 M  32
 2 24
2 16

.

:
 Adder / Subtractor

Incrementer

Memory Integer multiply

Logic unit

Shift unit

Processor
registers Floating point
Adder / subtractor

Floating point
multiply

Floating point
divide

Execution unit
 Performance for entire task using improved machine
Performance for entire task using old machine

Execution time for entire task using old machine

Execution time for entire task using improved machine

60 %

Speed up enhanced

Speed up enhanced

(Fe ) (S e )
Execution time old E
 TO
Execution time new E TN

 F 
E TN E TO  (1  Fe )  e 
 S e

E TO 1

 F  Fe
E TO  (1  Fe )  e  (1  Fe ) 
 Se  Se

1
Fe
(1 – Fe ) 
Se
1

Fe
(1 – Fe ) 
100
  F 
90  (1 – Fe )  e 
 100 
0.9  [100 – 99Fe ]
89

891
.

20  20

Execution time affected by improvement

Amout of improvement

400t
 20t
10

400t
 20t
50





 1600t
 20t
10

1600t
 20t
50

 9 
  100 
 10 
 3115
. 
  100 
 50 

10  10

Execution time affected by improvement

Amout of improvement

100 t
 10 t
10

100 t
 10 t
40
 


400 t
 10 t
10

400 t
 10 t
40

 8.2 
  100 
 10 
 20.5 
  100 
 40 

 

S tot
1
S tot
(X S  (1 – X))

1
(1 – 0.25)

1
 S INT
[(0.2 1.33)  (1 – 0.2)]
 6 s
5 s

1
S IO
[(0.35 1.2)  (1 – 0.35)]

 1536 t 64 t 
 , 
 49 1 

1620 t
84t

1536t
49

 1440t 160t 
 , 
 49 1 

1620 t
180t
 1440 t
49

Instruction stream
Processor Memory
(P) Data stream (M)
 IS
Instruction stream

Control IS Processor DS Memory

unit unit module
Instruction Data
stream stream

IS
Instruction stream

Data stream
Processor 1
unit Memory
1 module
1

IS Data stream
Instruction Processor 2
Control Memory
unit
unit module
stream 2
2

Data stream
Processor n Memory
unit module
n n

Shared memory
 Data stream

IS1 Control Instruction stream 1 Processor

unit unit
1 1

Shared memory

IS2 Control Instruction stream 2 Processor Memory Memory

Memory
unit unit module module
module
2 2 1 n
2

ISn Control Instruction stream n Processor

unit unit
n n

Data stream
Instruction stream n
Instruction stream 2
Instruction stream 1
IS1 Control Data stream 1
Instruction stream 1 Processor
unit unit Memory IS1
1 1 module
1

IS2 Control Instruction stream 2 Processor Data stream 2 IS2

Memory
unit unit
module
2 2
2

ISn Control Instruction stream n Processor Data stream n Memory ISn

unit unit module
n n n

Instruction stream n
Instruction stream 2
Instruction stream 1

 I 1 , I 2 , I 3 , ....

Machines
I1 I1 I2 I3 I4 I1 I2 I3 I4

I1 I1 I1
Thread switching
I1 I2 from I1 to I2 I1
Thread switching
clk cycles

I3 from I2 to I3 I1
Thread switching
I4 from I3 to I4
Thread switching Thread switching
I1 from I4 to I1 I2
Thread switching
I1 I2 from I1 to I2 I2

(a) Signal - threaded (b) Interleaved multithreading (c) Blocked multithreading

scalar scalar scalar
 I1 I1 I2 I3 I4 I1 I2 I3 I4

I1 I1 I1 I1 I1 I1

I1 I2 I2 I2 I1 I1

Thread switching

Thread switching
I3

I1 I1 I1 I1 I4 I4 I4 I4 I2 I2 I2

I1 I1 I2

I1 I1 I1 I2 I3

(a) Superscalar (b) Interleaved multithreading (c) Blocked multithreading

superscalar superscalar

I1 I1 I2 I3 I4 I1 I2 I3 I4

I1 I1 X X I1 I1 X X I1 I1 X X

I1 X X X I2 I2 I2 X I1 I1 X X
Thread switching

Thread switching
Delay I3
cycle X X X

I1 I1 I1 I1 I4 I4 I4 I4 I2 I2 I2 X

I1 I1 X X I2 X X X

I1 I1 I1 X I2 X X X I3 X X X

(d) VLIW (e) Interleaved multithreading (f) Blocked multithreading

VLIW VLIW
 I1 I2 I3 I4 I1 I2 I3 I4

I1 I1 I1 I1 I2 I2 I2 I3 I1 I1 I2 I2 I3

I4 I4 I4 I1 I1 I1 I2 I4 I1 I2 I2 I4 I4

I4 I4 I4 I1 I1 I1 I2 I3 I2 I4

I2 I4 I1 I1 I1 I1 I2 I2 I1 I1 I3 I4 I4

I3 I4 I4 I1 I1 I1 I1 I1 I2 I2 I3 I3 I4 I4

I1 I2 I2 I4 I4 I4 I4 I4 I1 I1 I2 I3 I3 I4

(a) Simultaneous multithreading (b) Chip multiprocessor

(SMT) (Multicore)
Hyperthreaded
processor Processor 1 Processor 2

Logical Registers ALU Registers ALU

processor 1
Fetch/ Fetch/
Logical
decode decode
processor 2
unit unit
Shared CPU
components L1 Cache L1 Cache

Shared logical Multiple

processor on L2 L2 processors on
FSB same chip Cache Cache separate chip
FSB

(a) Type 1 (b) Type 2

Multicore (CMP)

Registers ALU Registers ALU

Fetch/ Fetch/
decode decode
unit unit

L1 Cache L1 Cache

L2 L2 Multiple
Cache Cache processors in
FSB a package (chip)

(c) Type 3
Processor Processor Processor

Cache Cache Cache

Interconnection Network

Memory I/O
 Processor Processor Processor
and and and
caches caches caches

Memory I/O Memory I/O Memory I/O

Interconnection network
 CPU

PCIe
North bridge Chipset GPU

DRAM
GPU memory

Multiprocessor
SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

SP SP SP SP SP SP SP SP

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

 Instruction register

SIMD Lanes
(Thread
Processors)

Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg.

1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
(32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit) (32-bit)

Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load
store store store store store store store store store store store store store store store store
unit unit unit unit unit unit unit unit unit unit unit unit unit unit unit unit

Address combining unit Interconnection network

Local memory To
64 KiB Global Memory

* Reg : Registers
CUDA Thread

Per-CUDA thread private memory

Thread block

Per-block
local memory

Grid 0 Sequence

...
GPU
Inter-grid synchronization memory
Grid 1

...
Processor Processor  Processor

Cache Cache  Cache

Memory Memory  Memory

Interconnection Network
 Message (send / Receive)
Processor A Processor B
(Communication channel)
 Memory I/O
Processor processor
module

Memory I/O
Processor processor
module
 Bus Control I/O Memory I/O
logic Processor processor
modifier module devices

I/O Memory Memory

processor Processor
module module

Memory I/O
Processor Processor processor
module
 M0 M1 MM–1

P0
I/O0

PP–1
I/OC–1

Data
n
Data
RD/WR Multiplexer
2 modules From P0 – PP–1
RD / WR
addr
m
addr

Memory
module 4 Control
REQ0
ACK0
Memory
REQ1
enable Arbitration ACK1
module

REQP–1
ACKP–1
 Processor Processor
0 1

Memory Memory Memory Memory

module module module module
0 1 2 3

I/O unit I/O unit

0 1
 Processor Processor
0 1

Memory Memory Memory Memory

module module module module
0 1 2 3

I/O unit I/O unit

0 1
 

CA CB

A 0 A 0

B 1 B 1

CA = 0 CA = 1
A connected to 0 A connected to 1

A 0 A 0

B 1 B 1

CB = 0 CB = 1
B connected to 0 B connected to 1


 Level 2 MM : Memory module
0
000 MM 1

Level 1
1
0 001 MM 2

0
Level 0 010 MM 3
0
PA
1
011 MM 4
1
PB

0
100 MM 5

1
0 101 MM 6

0
110 MM7

1
111 MM 8




 
 
n 1
log n2 log 2


Source Level 0 Level 1 Level 2
Destination
0 000
1

001

2 010

3
011

4 100

5
101

110

6
7 111


 011 111
01 10

001 101

010 110

00 11 000 100

(a) 2 - cube (b) 3 - cube

0011 0111 1011 1111

0001
0101 1001 1101

0010 0110 1010 1110

0000 1000 1100

0100

(c) 4 - cube

Semester - III (ECE)
(2 1) (1 2) (2 3)
(4 1) (1 2) (1 3)
 Multiplicand : 0 1 1 0 1 +13

Multiplier : 0 0 1 1 0 6
1 1 0 1 0 –6 (2's complement form)

implied zero
1 1 0 1 0 0 multiplier
0 –1 +1 –1 0 Recoded multiplier

0 1 1 0 1 Multiplicand
0 –1 +1 –1 0 Recoded multiplier
Sign 0 0 0 0 0 0 0 0 0
extension 2's complement of multiplicand
+ 1 1 1 1 0 0 1 1
+ 0 0 0 1 1 0 1
+ 1 1 0 0 1 1 2's complement of multiplicand
+ 0 0 0 0 0
1 1 0 1 1 0 0 1 0 (– 78) in 2's complement form
 A Register Q Register
Initially 0 0 0 0 0 1 1 0 0 Dividend

Left shift A,Q 0 0 0 0 1 1 0 0

Subtract B 1 1 1 0 1
1 1 1 1 0 First cycle

Restore (A+B) 0 0 0 1 1
1 0 0 0
0 0 0 0 1

Left shift A,Q 0 0 0 1 1 0 0 0

Subtract B 1 1 1 0 1
0 0 0 0 0 Second cycle

0 0 0 1

Left shift A,Q 0 0 0 0 0 0 0 1

Subtract B 1 1 1 0 1
1 1 1 0 1 Third cycle

Restore (A+B) 0 0 0 0 0 0 0 1 0

Left shift A,Q 0 0 0 0 0 0 1 0

Subtract B 1 1 1 0 1
1 1 1 0 1 Fourth cycle

0 0 0 0 0
Restore (A+B) 0 1 0 0
Remainder
Quotient
 A Register Q Register
Initially 0 0 0 0 0 1 1 0 0 Dividend

Left shift A, Q 0 0 0 0 1 1 0 0

Subtract B 1 1 1 0 1 First cycle

1 1 1 1 0 1 0 0 0

Left shift A, Q 1 1 1 0 1 0 0 0
Add B 0 0 0 1 1 Second cycle
0 0 0 0 0 0 0 0 1

Left shift A, Q 0 0 0 0 0 0 0 1
Subtract B 1 1 1 0 1 Third cycle

1 1 1 0 1 0 0 1 0

Left shift A, Q 1 1 0 1 0 0 1 0
Add B 0 0 0 1 1 Fourth cycle

1 1 1 0 1 0 1 0 0

Quotient
1 1 1 0 1
Add B 0 0 0 1 1 Restore
remainder
0 0 0 0 0
Semester - III ( CSE / IT )
Semester - III ( CSE / IT ) - Regulation 2013
Semester - VI (ECE) - Regulation 2013 57241
Semester - III (CSE/IT) - Regulation 2013
Semester - VI (ECE)
 Semester - VI (ECE)
Semester - III (CSE/IT) - Regulation 2013

(11010) 2 – (10000) 2
1 st

4
1.04
6
1.19
 Semester - VI (ECE)
Semester - III (CSE/IT) - Regulation 2013

(11011) 2 – (10011) 2
(1001010) 2 (1000) 2
( 0.5) 10 (0.4375) 10
1
2
( 0.5) 10 (0.4375) 10
1
2
 Semester - VI (ECE)
Semester - III (CSE/IT) - Regulation 2013

(– 0.75) 10
( 075
. ) 10 (– 0.275) 10
Semester - III (CSE/IT), V (ECE) - Regulation 2013

0.4 10 0.6
0.4 0.6
1.0 10 6
 ( 34) 10
(1011110) 2 ( 22) 10 ( 0010110) 2
Semester - V (ECE) - Regulation 2017
(11010) 2 – (10000) 2

(–10 –10 100) 10