Module 4

Intel 80386 Processor

 Two versions of 80386 are commonly available:

80386DX 80386SX
32-bit address bus 24-bit address bus
32-bit data bus 16-bit data bus
Address 4GB of memory Address 16MB of memory
➢ 32-bit processor, it has 32-bit ALU which allows to process 32-bit data
at a time.
➢ 32-bit address bus, therefore it can access 4GB physical memory and
64Terabytes of Virtual memory.
➢ It has pipeline architecture which allows simultaneous instruction
fetching, decoding, and executing and memory management.
➢ Because of instruction pipelining higher bus bandwidth & on chip
address translation mechanism, the average execution time has been
significantly reduced.
➢ It allows user to switch between different OS such as DOS and UNIX
➢ It operates in Real, Protected and Virtual 8086 mode.
➢ It is compatible with 8086, 8088, 80186, 80286 architecture.
➢ It has different data types like bits, byte, word, double word, Quadword,
Tenbytes integer (signed and unsigned form).
➢ It has separate pins for its address and data line, this result in higher
performance and easier hardware design.
➢ Prefetch unit permits to prefetch up to 16-bytes of instruction code.
Therefore, fetch time for most of the instruction is hidden and therefore
increase the performance.
➢ 16 to 20 MHz operation therefore provides 10 times higher performance
than that of a standard 5 MHz 8086 processor.
➢ High speed numeric support using 80387 coprocessor.
The Internal Architecture of 80386 is divided into 3 sections.

➢Central processing unit(CPU)

▪ Execution Unit
▪ Instruction Unit

➢Memory management unit(MMU)

▪ Segmentation Unit
▪ Paging Unit

➢Bus interface unit(BIU)

Bus Interface Unit -
• This unit is responsible for transferring data in and out of the microprocessor.
• It is connected to the external memory and I/O devices, using the system bus.
• It gets requests from Prefetch unit for fetching instructions and from execution unit
for transferring data.
• If both requests occur simultaneously preference is given to execution uni.

Prefetch Unit -
• This unit fetches further instructions in advance to implement pipelining.
• It fetches the next 16 bytes of the program and stores it into the Prefetch Queue.
• It refills the queue when at least 4 bytes are empty as 80386 has a 32-bit data bus.
• During a branch, the instructions in the queue are invalid and hence are discarded.
Decode Unit -
• 80386 microprocessors have a separate unit for decoding instructions called the Decode
Unit.
• It decodes the next three instructions and keeps them ready in the Decode Queue.
• The decoded instructions are stored in Micro-Coded form.
• During a branch, the instructions in the queue are invalid and hence are discarded.
Execution Unit -
• This unit performs the main task of executing instructions.
• Normally, execution requires Arithmetic and Logic operations performed by a 32-bit ALU.
• It also has dedicated circuits for 32-bit multiplication and division.
• A 64-bit barrel shifter is also provided for faster shifts during multiplication and division.
• Operands for the ALU can either be provided in the instruction, or can be taken from
memory or could be taken from the 32-bit registers like EAX, EBX etc.
• Additionally, there is a 32-bit Flag register (EFLAG) giving the status of the current result.
Memory Unit -
• This unit converts Virtual address (Logical address) to Physical address.
• 80386 microprocessor implements 64 Terra bytes of Virtual memory using
Segmentation and Paging. Hence the memory unit is sub-divided into
Segmentation unit and Paging unit.
• Segmentation is compulsory, while aging is optional.
• The Segmentation unit converts the Logical address into a Linear address.
• The Paging unit converts the Linear address into a Physical address.
• If Paging is not used, then the Linear address itself is the Physical address.
General-Purpose Registers:
The 80386 has eight 32-bit general-purpose registers named EAX, EBX, ECX, EDX,
ESI, EDI, EBP, and ESP.
These registers can be used for various arithmetic and logical operations, address
calculations, and data manipulation.

Index Registers:
The 80386 has two index registers, ESI (Extended Source Index) and EDI (Extended
Destination Index), which are primarily used for string manipulation instructions.
Base Pointer (BP) and Stack Pointer (SP):
The 80386 includes two special-purpose 32-bit registers, EBP (Extended Base Pointer)
and ESP (Extended Stack Pointer).
EBP is typically used to reference parameters and local variables in function calls
within high-level programming languages like C.
ESP points to the top of the stack and is used for managing the stack in subroutine calls
and returns.

Instruction Pointer (IP):

The 80386 includes a 32-bit instruction pointer register, EIP (Extended Instruction
Pointer), which holds the offset address of the next instruction to be executed.
Segment Registers:
The 80386 has six segment registers:
CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES (Extra Segment), FS,
and GS.
These registers are used to point to different segments of memory, facilitating memory
addressing in segmented memory models.

Flags Register:
The 80386 features a 32-bit flags register, EFLAGS, which contains various status and
control flags that reflect the outcome of arithmetic and logical operations, control the
processor's operation, and indicate conditions such as carry, zero, overflow, and
direction.
Control Registers:
The 80386 includes several control registers such as CR0, CR2, CR3, and CR4, which
are used for controlling various aspects of the processor's operation, including paging,
protection, and debugging.

Debug Registers:
The 80386 also includes debug registers DR0 through DR7, which are used for
debugging purposes, allowing developers to set breakpoints, watchpoints, and control
program execution during debugging sessions.
Flag Register of 80386

• The Flag register of 80386 is a 32-bit register.

• Out of the 32-bits, Intel has reserved bits D18 to D31, D5 and D3.
• D1 is always set at 1.
Carry Flag (CF):
• Indicates whether arithmetic carry or borrow occurred in arithmetic operations.
• For example, it gets set if an addition operation produces a carry or if a subtraction
operation requires a borrow.
• Used for unsigned arithmetic operations and shifts.
Zero Flag (ZF):
• Indicates whether the result of an operation is zero.
• Set if the result of an operation is zero; otherwise, it is cleared.
• Useful for conditional branching and comparing values.
Sign Flag (SF):
• Reflects the sign of the result of an arithmetic or logical operation.
• Set if the most significant bit of the result is set (indicating a negative result);
otherwise, it is cleared.
Overflow Flag (OF):
• Indicates whether signed arithmetic overflow occurred.
• Set if the result of a signed arithmetic operation is too large to be represented in the
destination operand size (e.g., 32 bits).
• Useful for detecting errors in signed arithmetic operations.

Direction Flag (DF):

• Controls the direction in which string operations (e.g., MOVSB, MOVSW) move
data.
• If set, string operations decrement the index registers (ESI and EDI); if cleared, they
increment them.
Interrupt Enable Flag (IF):
• Controls the response of the processor to interrupts.
• If set, interrupts are enabled, allowing the processor to respond to external interrupt
requests.
• If cleared, interrupts are disabled, preventing the processor from responding to
external interrupts.

Trap Flag (TF):

• Used for single stepping through code during debugging.
• If set, the processor executes one instruction and then generates a trap (interrupt),
allowing debuggers to examine the state of the processor after each instruction.
VM (Virtual Mode Flag):

• The VM flag is a control flag in the EFLAGS register of the 80386 processor.
• It indicates whether the processor is operating in virtual 8086 mode.
• When set, the processor operates in virtual 8086 mode, allowing multiple virtual
8086 environments to run concurrently on a single 80386 processor.
• Virtual 8086 mode enables running legacy 16-bit applications in a protected
environment, providing memory protection and multitasking capabilities.
RF (Resume Flag):
• The RF flag is a control flag in the EFLAGS register of the 80386 processor.
• It is used in conjunction with debugging features.
• When set, the RF flag allows the processor to automatically restart the execution of
instructions after a debug exception.
• This flag can be useful for debugging purposes to resume execution without manually
restarting the program.
NT (Nested Task Flag):
• The NT flag is a control flag in the EFLAGS register of the 80386 processor.
• It is used in conjunction with task switching and multitasking features.
• When set, the NT flag indicates that the current task has been nested into another task.
• Nested tasks are used in certain multitasking scenarios where one task initiates the
execution of another task while maintaining control over the system.
IOPL (I/O Privilege Level):
• The IOPL flag is a control flag in the EFLAGS register of the 80386 processor.
• It is part of the system privilege level mechanism for controlling access to I/O
instructions.
• The IOPL flag specifies the privilege level required to execute I/O instructions.
• It consists of two bits, allowing four privilege levels (0 to 3), with higher numbers
indicating higher privilege.
• Access to I/O instructions is restricted based on the privilege level of the executing
code and the value of the IOPL flag.
Control Register 0 (CR0)
It is a 32-bit register that controls various operating modes and features of the processor.
It holds several control flags, each of which enables or disables specific processor
features. The flags contained within CR0 are -
PG (Paging):
• The PG bit enables or disables paging, a memory management scheme that allows the
processor to use virtual memory.
• When the PG bit is set (1), paging is enabled, and the processor uses the page
translation mechanism to map linear addresses to physical addresses.
• When the PG bit is cleared (0), paging is disabled, and linear addresses directly
correspond to physical addresses.
ET (Extension Type):
• The ET bit is reserved and not used in the 80386 processor. It should be set to 0.
TS (Task Switched):
• The TS bit is used in conjunction with hardware task switching.
• When the TS bit is set (1), it indicates that the processor has experienced a task
switch.
• This flag is primarily used in multitasking environments to track when the processor
switches between different tasks.
EM (Emulation):
• The EM bit is reserved and not used in the 80386 processor. It should be set to 0.
MP (Monitor Coprocessor):

• The MP bit controls the operation of the built-in Floating-Point Unit (FPU) or coprocessor.
• When the MP bit is set (1), it indicates that an FPU or coprocessor is present and
operational.
• When the MP bit is cleared (0), it indicates that no coprocessor is present, and the
processor should emulate FPU instructions using software.
PE (Protection Enable):
• The PE bit enables or disables Protected Mode, an operating mode that provides memory
protection and multitasking capabilities.
• When the PE bit is set (1), Protected Mode is enabled, and the processor operates in a
protected environment with memory segmentation and privilege levels.
• When the PE bit is cleared (0), the processor operates in Real Mode, a simpler operating
mode without memory protection or multitasking features.
Control Register 1 (CR1)
• Reserved by Intel

Control Register 2 (CR2)

• CR2 is a control register used for managing page faults and page-level protection.
• It holds the linear address of the last page fault that occurred in the system.
• When a page fault occurs during memory access, the processor automatically
saves the linear address of the faulting memory location into CR2.
Control Register 3 (CR3)
• CR3 is a control register used for managing the page directory base address.
• In systems with paging enabled (PG bit set in CR0), CR3 holds the physical base
address of the page directory, which is a data structure used for translating linear
addresses to physical addresses.
• The processor uses CR3 in conjunction with other page directory and page table
structures to perform address translation during memory access.
Determine the features that are accessible.
There are 3 processing modes –
➢Real mode
➢Protected mode
➢Virtual 8086 mode

Real Mode
The 80386 microprocessor is capable of operating in multiple modes, including Real
Mode, Protected Mode, and Virtual 8086 Mode. However, upon reset, it always starts
in Real Mode, which is the simplest and most backward-compatible mode.
1. Characteristics of Real Mode in 80386
Real Mode in 80386 operates similarly to the 8086 and 8088 microprocessors, with the
following key features:

a. 20-bit Addressing (1MB Memory Limit)

• In Real Mode, 80386 can address only 1MB of memory (from 00000H to FFFFFH)
because it uses 20-bit physical addresses.
• Physical address is computed using the Segment:Offset addressing method, just
like in 8086:
Physical Address = (Segment × 10H) + Offset
• Since segment registers are 16-bit, the highest address is:
FFFFH × 10H + FFFFH = FFFFFH
b. 16-bit Registers and Instruction Set
• The CPU functions like an 8086 processor, with 16-bit registers and 16-bit

instructions.
• Even though 80386 has 32-bit registers, they remain inaccessible in Real Mode.

c. No Memory Protection
• Since Real Mode is designed for backward compatibility with the 8086, it does not

support memory protection.

• Any program can access any part of memory, which can lead to system crashes if

one program overwrites another's data.

d. No Multitasking
• The 80386 does not support multitasking in Real Mode.

• Only one program runs at a time, without process isolation.

e. I/O and Interrupt Handling
• Direct hardware access: Programs can directly access I/O ports using

instructions like IN and OUT.

• Interrupt handling works just like in 8086, with support for hardware (INTR,

NMI) and software interrupts (INT, INTO, IRET).

2. Advantages of Real Mode

• Backward compatibility: Allows running 8086/8088 programs without
modification.
• Simple memory model: No segmentation complexity like in Protected Mode.
• Easy hardware interfacing: Direct access to memory and I/O port
3. Limitations of Real Mode
Feature Real Mode Limitation
Memory Access Limited to 1MB (20-bit addressing)

Memory Protection No protection, programs can overwrite each other

Multitasking Not supported, only one program runs at a time

32-bit Features Unavailable, operates in 16-bit mode

Paging Not available, requires Protected Mode

4. Transition from Real Mode to Protected Mode
To switch from Real Mode to Protected Mode (which unlocks 32-bit registers,
paging, and multitasking), the following steps are needed:
1. Set the PE (Protection Enable) bit in the Control Register (CR0).
2. Load a valid Global Descriptor Table (GDT).
3. Enable segment descriptors.
4. Jump to a 32-bit protected mode instruction.
The 80386-microprocessor introduced Protected Mode, which significantly enhances
memory management, multitasking, and system security compared to Real Mode.
This mode is used in modern operating systems such as Windows, Linux, and UNIX-
based systems.

1. Features of Protected Mode in 80386

Protected Mode overcomes the limitations of Real Mode and offers full access to the 32-
bit architecture of 80386.

a. 32-bit Addressing (4GB Memory)

• Unlike Real Mode, which is limited to 1MB memory, Protected Mode can

address up to 4GB of memory (2³² bytes).

• It uses segment descriptors instead of direct segment:offset addressing.
b. Memory Protection
• Each program runs in a separate protected memory space, preventing one

program from accidentally modifying another's memory.

• Segmentation and paging allow fine-grained control over memory access.

c. Virtual Memory Support

• The 80386 supports virtual memory, which allows using disk space as additional

memory.
• This enables execution of programs larger than available physical RAM.

d. Multitasking
• Multiple programs (processes) can run simultaneously, with the CPU switching

between tasks.
• Each task has its own Task State Segment (TSS), which saves CPU registers and

other context data.

e. Privilege Levels (Ring Protection)
• Four privilege levels (Rings 0–3) define who can access what resources:

o Ring 0 (Kernel Mode) → OS and device drivers (full access).

o Ring 1, Ring 2 → Reserved for OS use.

o Ring 3 (User Mode) → Applications with restricted access.

• Prevents user programs from modifying system resources.

f. Segmentation and Paging
• Segmentation:

o Instead of segment:offset addressing, Protected Mode uses segment

descriptors in a Global Descriptor Table (GDT).

o Segments define access rights, base address, and limit.

• Paging:

o Enables 4KB pages, translating logical addresses into physical addresses.

o Supports demand paging, which loads data into memory only when needed.

2. How to Switch from Real Mode to Protected Mode

To enable Protected Mode, the following steps are required:
1. Disable interrupts to avoid conflicts during transition.
2. Load the Global Descriptor Table (GDT) with segment descriptors.
3. Set the PE (Protection Enable) bit in CR0 register.
4. Perform a far jump to a Protected Mode segment.
5. Enable Paging (optional) for virtual memory.
3. Advantages of Protected Mode

Feature Benefit
Memory Access Supports 4GB (2³² bytes) addressing

Memory Protection Prevents programs from corrupting each other

Multitasking Allows multiple applications to run simultaneously

Paging Support Enables virtual memory and efficient memory use

32-bit Registers Uses full 32-bit architecture for better performance
Hardware Privilege Levels Enhances system security with Ring 0 to Ring 3
The 80386 microprocessor introduces Virtual 8086 Mode (VM86) as a sub-mode of
Protected Mode. This mode allows the execution of 8086 programs while taking
advantage of the memory protection and multitasking features of Protected Mode.
1. Features of Virtual 8086 Mode

a. 8086 Compatibility
• Allows execution of 8086 programs inside a protected-mode operating system.

• Each VM86 task behaves like a separate 8086 processor, enabling multiple DOS

applications to run simultaneously.

b. 1MB Addressing (20-bit Address Space)

• Uses segmented memory addressing like Real Mode.

• Memory is limited to 1MB (00000H – FFFFFH) per virtual machine.

c. Runs in Protected Mode
• Unlike Real Mode, Virtual 8086 Mode operates inside Protected Mode, so it
benefits from multitasking and memory protection.

d. Multiple Virtual Machines

• The 80386-microprocessor can create multiple virtual 8086 environments,
allowing multiple DOS applications to run at the same time.

e. Memory Protection & Paging Support

• VM86 mode can use paging, meaning virtual addresses can be mapped
anywhere in the system memory.
• The operating system controls access, preventing one VM86 task from
interfering with another.
2. How Virtual 8086 Mode Works
1. The CPU is in Protected Mode, but a task is set to Virtual 8086 Mode using a
bit in the EFLAGS register (VM = 1).
2. The task runs 8086 instructions in a virtualized environment.
3. The paging mechanism allows the virtualized program to think it's accessing
memory normally.
4. I/O and interrupt handling can be controlled by the operating system.
3. Advantages of Virtual 8086 Mode
Feature Benefit
Backward Compatibility Runs legacy 8086/DOS programs in Protected Mode
Multitasking Multiple 8086 tasks can run simultaneously
Memory Protection Each VM86 program runs in isolated memory
Paging Support Can map memory beyond 1MB using paging
Efficient Hardware No need for separate 8086 hardware
Utilization
 4. Limitations of Virtual 8086 Mode

Limitation Description
Limited to 1MB Each VM86 task can only access 1MB of memory (like Real
Mode)
No Direct Hardware The OS must trap and emulate I/O requests, adding overhead
Access
Privileged Instructions Certain 8086 instructions (e.g., CLI, STI) are not allowed directly
Restricted

Performance Overhead Virtualization adds performance overhead compared to Real

Mode
Segment and Page translation mechanism

The 80386 microprocessor supports two key memory management mechanisms:

1. Segmentation – Divides memory into logical segments.
2. Paging – Divides memory into fixed-size pages for efficient memory
management.

Both mechanisms work together in Protected Mode to provide address translation,

memory protection, and virtual memory support.
1. Segmentation in 80386

a.Concept of Segmentation
• In segmentation, memory is divided into segments, each with a base address, size (limit),
and access rights.
• Logical addresses (also called virtual addresses) are represented as Segment
Selector:Offset.
• The CPU translates this logical address into a linear address using segment descriptors
stored in a Descriptor Table (GDT/LDT).
b. Descriptor Tables
• Global Descriptor Table (GDT) →Used by the OS for system-wide memory segmentation.

• Local Descriptor Table (LDT) → Used by processes for private memory segmentation.

• Segment Descriptor contains:

o Base Address (starting address of the segment).

o Limit (size of the segment).

o Access Rights (privilege level, read/write permissions, etc.).

c. Logical to Linear Address Translation (Segmentation)

1. CPU takes the Segment Selector (from CS, DS, SS, etc.) and fetches the Base Address
from the Descriptor Table.
2. Linear Address is calculated as: Linear Address = Segment Base + Offset
3. If paging is disabled, this linear address becomes the physical address.
Example Calculation:
• Segment Base = 00400000H

• Offset = 00001234H

• Linear Address = 00400000H + 00001234H = 00401234H

2. Paging in 80386
a. Concept of Paging
• Paging allows memory to be divided into fixed-size 4KB pages.

• Linear addresses from segmentation are further mapped to physical addresses

using Page Tables.

• This enables virtual memory and efficient memory management.

b. Page Tables
Paging uses two levels of tables:
1. Page Directory Table (PDT) → Contains 1024 Page Directory Entries (PDEs),
each pointing to a Page Table.
2. Page Table (PT) → Contains 1024 Page Table Entries (PTEs), each pointing to
a 4KB Page Frame in RAM.
Each page entry contains:
• Page Frame Address (Physical memory location).

• Access Control Bits (Read/Write, Supervisor/User, Present/Absent).

c. Linear to Physical Address Translation (Paging)
1. Linear Address is divided into three parts:
• Page Directory Index (PDI) (Top 10 bits) → Selects a Page Directory Entry.

• Page Table Index (PTI) (Next 10 bits) → Selects a Page Table Entry.

• Offset (Lowest 12 bits) → Determines the exact byte within the 4KB page.

2. Steps of Translation:
• CPU uses CR3 (Page Directory Base Register) to find the Page Directory

Table.
• From Page Directory Entry (PDE), it gets the address of the required Page

Table.
• From Page Table Entry (PTE), it fetches the Physical Address of the page

frame.
• Final Physical Address = Page Frame Base + Offset.
Example Calculation:
• Linear Address = 00401234H

o PDI (10 bits) → 0000000000

o PTI (10 bits) → 0000000001

o Offset (12 bits) → 000000000100

• The final physical address is calculated as:

Physical Address = Page Frame Base + Offset

= 00005000H + 00000004H = 00005004H
• CPU translates this to a physical address using Page Tables.

3. Combined Segmentation and Paging

• Segmentation translates a logical address to a linear address.
• Paging translates a linear address to a physical address.
• This allows the 80386 to efficiently manage large virtual memory spaces while
ensuring protection and isolation between processes.
 4. Advantages of Segmentation & Paging in 80386

Feature Segmentation Paging

Memory Provides logical separation of Manages memory in fixed-size pages

Management code, data, and stack. (efficient use).
Protection Each segment has access rights. Prevents programs from accessing
memory outside their allocated pages.
Address Logical to Linear address Linear to Physical address conversion.
Translation conversion.
Virtual Allows large memory models but Supports Virtual Memory (swap pages
Memory requires large segment tables. in/out from disk).
May-2023
1) Discuss in brief the protection mechanism of 80386DX. (5m)
2) Explain the Register organization of 80386. (10m)
December 2022
1) Differentiate between Real Mode, Virtual Mode, and Protected Mode of 80386 Processor.
(5m)
2) Explain the segment descriptor of 80386 processor (10m)
3) Explain the EFLAG REGISTER of 80386 processor. (10m)
December 2019
1) Explain VM, RF, IOPL, NT and TF flags of 80386 microprocessor. (5)
2) Differentiate Real Mode, Protected Mode, and Virtual Mode of 80386 microprocessor. (5m)
May-2019
1) Explain VM, RF, IOPL, NT and TF flags of 80386 microprocessor. (5m)
2) Differentiate Real Mode, Protected Mode, and Virtual Mode of 80386 microprocessor. (10m)
December-2018
1) Explain the FLAG REGISTER of 80386 processor. (5m)
2) Explain the modes of operation of 80386 microprocessor. (10m)