PCIE SYLLABUS:
PCIE TRAINING TOPICS:
Session 1: Background
1. PCI-X Introduction and architecture
2. Drawback of the PCI and PCI-X.
3. PCIe Protocol Overview
4. Serial and Parallel Protocol
5. Limitation of the PCI parallel Bus protocol.
Session 2: PCIe Architecture Overview
1. How PCIe evolved
2. Difference b/w PCI and PCIe
3. PCIe Topology
4. PCIe Throughput
5. Device layer architecture (3-layer architecture).
6. packet flow through the layer’s overviews only.
7. Major functionality of each layer (transaction, datalink, physical layer).
Session 3: Configuration Overview
1. What is meant by BDF
2. PCI-Compatible Space
3. Extended Configuration Space.
4. Single-host and multi-host system (Differences).
5. Configuration Requests (type0 and type1)
6. Enumeration
Session 4: Address Space & Transaction Routing.
1. Base address registers (BARs).
2. Configuration Space access: CAM, ECAM
3. Type0 header and Type1 header
4. BAR configuration in type1 and type0 Headers.
5. Base and Limit Registers in the Headers.
6. Registers Used for Address Routing.
Session 5: TLP Routing Basics
1. ID Routing (ARI), Transaction Layer Feature
2. Explanation about packet-based protocol
3. Header Format/Type Field Encodings of TLP
4. Different types of TLP (Memory, Atomic, IO, Config, Message)
5. Completion TLP Type, Completion Timeout
6. TLP Prefix Rules, TLP ordering Rules, ECRC error handling
7. Header format of the TLP (3DW and 4 DW differences).
8. Memory request TLP format and full flow through the layers
Session 6: Flow Control in transaction layer
1. Flow Control Buffers and Credits.
2. Flow control Example, update FC frequency
3. Flow Control Initialization (DLCMSM state machine).
4. flow control mechanism working
5. Quality of Service (VC arbitration, Port arbitration)
6. Explain about Traffic class and virtual channels.
7. What is meant by TC-VC mapping and why we need that.
8. Port arbitration (switch and multifunction devices)
Session 7: Transaction Ordering
1. Ordering Rules and Traffic Classes (TCs).
2. Data link layer
3. DLLP Types, DLL Data integrity
4. Generic Data Link Layer Packet Format.
5. Different types of DLLPs and functionality.
6. Difference between TLP and DLLP.
7. ACK/NACK Protocol working using DLLPs
Session 8A: Physical Layer ‐ Logical (Gen1 and Gen2).
1. Physical Layer Overview
2. Transmit Logic Overview
3. Receive Logic Overview
4. Packet Format Rules
5. mux, Byte Striping, Scrambler Algorithm, 8b/10b Encoding, Differential Driver
Session 8B: Physical Layer ‐ Logical (Gen1 and Gen2).
1. Receiver Logic’s Front End Per Lane.
2. Lane-to-Lane Skew
3. 8b/10b Decoder (disparity calculation).
4. Byte Un-Striping
5. Descrambler
6. physical layer error handling
Session 9: Physical Layer ‐ Logical (Gen3)
1. Encoding for 8.0 GT/s
2. what is meant by Ordered Set Blocks (all types of overviews)
3. transmitter Framing Tokens.
4. Scrambling and scrambling rules
Session 10: Gen3 Physical Layer Receive Logic
1. Differential Receiver
2. Gen3 Physical Layer Receiver Details
3. Gen3 CDR Logic
4. Gen3 Elastic Buffer Logic
5. Physical Layer ‐ Electrical
6. Physical Layer Electrical Overview
7. Differential Transmitter/Receiver
8. Margining Voltage
Session 11: Physical Layer ‐ Electrical.
1. Transmission with De‐emphasis
2. Benefit of De‐emphasis at the Receiver
3. Three-Tap Tx Equalizer
4. The Eye Test
Session 12: Link Initialization & Training
1. Ordered Sets in Link Training (TS1 and TS2).
2. Link Training and Status State Machine (LTSSM).
3. Overview of each state in the LTSSM.
4. Detect State explanation
5. Polling State (each substate also explained).
Session 13: Link Training and Status State Machine (LTSSM).
1. Configuration State
2. Link and lane Number Negotiation.
3. Detailed Configuration Substates.
4. Recovery State
5. Detailed Recovery Substates.
Session 14: Recovery state
1. Recovery. Idle.
2. Other LTSSM states
3. L0 and L0s state
4. L1 and L2
5. Hot reset and loopback
6. Disable state
7. Condition for the FSM to go for each state.
Session 15: Error Detection and Handling
1. PCIe Error Reporting
2. Error Classes (Correctable Errors and uncorrectable).
3. fatal and non-fatal errors
4. PCIe Error Checking Mechanisms
5. Error Checks by Layer
6. Error‐Related Configuration Registers
7. How Errors are Reported
8. PCI-Compatible Error Reporting Mechanisms
9. Advanced Error Reporting (AER)
Session 16: Interrupt Support
1. Two Methods of Interrupt Delivery
2. The Legacy Model
3. Virtual INTx Signaling
4. INTx Message Format
5. Mapping and Collapsing INTx Messages
6. Register related to interruption.
Session 17: System Reset
1. Two Categories of System Reset
2. Fundamental Reset
3. Hot Reset (In-band Reset).
4. Function Level Reset (FLR)
Session 18A: Power Management
1. Introduction to PM and need of PM
2. System PM States
3. Device-Class-Specific PM Specs
4. How the LTSSM state affects while changing the device PM state.
5. Active State Power Management (ASPM).
6. Software Initiated Link Power Management
7. The PME Message
Session 19:
1. PIPE
2. Logic Protocol Analyzers
3. PCIe Gen4 Updates
Session 20:
• PCIe Soc and IP Level Verification
