TLP Elements (TL)

Sunday, October 22, 2023 1:06 PM

PCI Express is a high-speed serial connection that operates more like a network than a bus.
And finally, we have one DW of data. This is a good time to mention that PCIe runs big Endian, and Intel processors think lit tle
Endian. So if this was a regular PC computer, it was writing 0x78563412 in its software representation.

A write TLP operation is fire-and-forget (Posted)

A read operation, on the other hand, requires the Requester to wait for a Completion (non-Posted).

For Addresses below 4 GB, Requesters must use the 32-bit format. The behavior of the receiver is not specified if a 64-bit format
request addressing below 4 GB (i.e., with the upper 32 bits of address all 0) is received
end-to-end data integrity check provided through the ECRC

For example, to write 1 byte to address 0100 , 0x3567

0x3564 Address = 0x3564 (dword-aligned)
FBE = 4'b1000

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For example, to write 1 byte to address 0100 , 0x3567
0x3564 Address = 0x3564 (dword-aligned)
FBE = 4'b1000
LBE = 4'b0000 (if data 1DW must be 4'b0000)

if you want to write 27 bytes at address 6 4

➢ Address = 4
➢ Length = 7DW (7*4=28 B) 8
➢ End_address = # + start -1 = 32 12
➢ FBE = 4'b1100
16
➢ LBE = 4'b0001
20
24
28
32

PCI Express Primer #3: Transaction Layer

From <https://www.linkedin.com/pulse/pci-express-primer-3-transaction-layer-simon-southwell/>
Down to the TLP: How PCI express devices talk (Part II) | xillybus.com
linux - why PCIe TLP header has "Last DW BE" and "First DW BE"? - Stack Overflow

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TC/VC Mapping
Friday, October 27, 2023 2:10 PM

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In this example the upstream link has just acknowledged sequence 4. After this the downlink sends transactions 5, 6, 7
and 8. All four TLPs will remain in the retry buffer. When the upstream link sends an acknowledge DLLP back with
sequence number 7, TLPs 5 to 7 are acknowledged and are feed from the retry buffer, whilst TLP 8 remains, waiting to
be acknowledged.
2^12 = 4,096
The sequence numbers are 12 bits with a range in values of 0 to 4095. To ensure clean rollover, just as for flow control,
the maximum allowed unacknowledged packets is limited to half this range, at 2048, even if there are enough credits to
send additional TLPs. The data link layer will stop sending TLPs if this maximum is reached.
8*16 = 128

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Week Status
Friday, October 27, 2023 3:35 PM

1. Understood TC/VC Feature.

11

>> Transaction Descriptor

>> Flow Control
>> AXI Bus

(2*1024)/20 = 102.4
(4*1024)/20 = 204.8
20*128 = 2,560 /1024 = 2.5
2^8 = 256 /2 = 128

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Wireless Assignment
Saturday, October 28, 2023 3:16 PM

 Different handsets : AMPS and DAMPS

 Erleng-B

:average number of calls (poisson distribution)

h: average holding time for call (exponential distribution)

➢ Simulation Points ?

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➢ MATLAB Function for:
1. Passion Distribution
2. Exp Distribution

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PCIe Presentaion
Monday, October 30, 2023 3:20 PM

PCIe SIG Generation Figure:

Full-Duplex

Lane Definition

PCIe Topology and Component:

1. Root Complex: interface between the CPU and the rest of the system.
2. Switch: allow more PCIe devices to connected to the topology
3. Bridge: allow the interfaces with other buses like PCI and PCI-X to achieve the compatibility
4. Endpoint: they are peripheral devices such as Ethernet, USB or graphics devices.
5. Port is the interface between a PCIe component and the Link

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6.

Device Layers (outbound & inbound):

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Quick Notes Page 48
 Transaction layer:
a. The transaction layer is responsible for TLP (Transaction layer packets) assembly and disassembly creation and decoding.
b. The requests can be posted or non-posted.
c. The posted request means that the device targeted does not return a completion to the requester (fire and forget)
d. the non-posted request means that the device targeted return a completion to the requester
e. The transaction layer is also responsible for flow control functionality and transaction ordering functionality
f. The flow control functionality is that each device sends the amount of free space in its received buffer to the other device (Data Integrity).
➢ TLP assembly and disassembly
There are 4 categories of requests, The first three already handled by PCI and PCI -X but messages are new type for PCIe.
1. Memory requests: memory transactions include 2 classes, read requests with their completions and write requests. these types of transactions
are routed through memory addresses.
2. IO requests: IO transactions used for legacy devices.
3. 3. Configuration requests: configuration requests used to access the configuration space to access the device, include 2 types, type 0 everything
in the topologies of PCIe, except the switches and the bridges.
4. 4. Messages requests: Message request is a new type defined in PCIe, include Power management, Error signaling
5. Completions: completions are expected in response for non-posted requests

➢ Flow Control:
The flow control is a mechanism uses a credit-based mechanism that allow the transmitting port to be aware of buffer space available at the
receiving port, to sends the TLPs with no losses.
The credits are updates using the flow control DLLPs.
we need to notes that the flow control is a shared responsibility between the data link layer and the transaction layer, The data link layer sends
and the receive the information about the buffer space but the transaction layer contains the counter that counts the availab le space.

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