PCI-E

SION Semiconductors Pvt Ltd

• INTRODUCTION
• GENERATIONS OF PCIe
• FEATURES
• TOPOLOGY
• OVERVIEW OF PCIE LAYERS
• TRANSACTION LAYER
• DATA LINK LAYER
• PHYSICAL LAYER
Introduction
• PCIe stands for Peripheral Component Interconnect express.
• It is an interface used to connect high-speed Peripheral
components.
• PCIe is available in a different physical configuration which
includes x1, x4, x8, x16, x32.
• The motherboard has a number of PCIe slots to connect
different components such as GPU , Wi-Fi cards, SSD..
• PCIe is a replaced version of PCI(Peripheral component
interconnect).
• First PCIe was named as High-speed interconnect (HSI),then
renamed to 3GIO (3rd generation I/O) and finally renamed to
PCIe.
• PCIe is better than PCI and the differences are:
Generations of PCI-E
• Till now 6 generations of PCIe have been introduced in
the market.
• PCIe 1.0 to PCIe 4.0 are launched in the market.
FEATURES:
• It is a point to point configuration.
• It is a serial bus architecture which requires fewer pins than
parallel bus.
• It is a scalable.(Scalable means that if a single lane is able to
transfer the data 2GB/s than another lane can transfer 4GB/s. This
is the scaling of the bandwidth.)
• It is a packet based transaction protocol.
• PCIe has the same memory , I/O , Configuration address space as
PCI. The additional feature added to PCIE is messages.
• The data integrity and error handling capability of PCIe is better
than the PCI.
Topology:

• PCIe Topology will help to understand that how the different

peripherals devices will communicate with CPU through the PCIe link
•Link :
• PCIe works on the different lanes . The transaction speed of PCIe
is varying with different PCIe architecture
• CPU:
• The CPU can access endpoints through Root Complex and
Endpoints can communicate with CPU through Root complex.
• Root complex:
• The Root complex can directly access the memory. The PCIe
endpoints will communicate the CPU and the memory with help
of root complex.
• Endpoints:
• LEGACY ENDPOINTS : These are the device which supports I/O Requests
as a completer and generate I/O Requests.
• PCI-E ENDPOINT : These are the device which does not requires
I/O resources claimed through BAR(s) and must not generate I/O
Requests.
• Switch :
• It contains of multiple “virtual” PCI-to-PCI bridge devices.
• By using this we connect many PCIe endpoints with the help of PCIe Switches.
• A switch may only forward peer-to-peer transactions between two downstream ports.

• PCI Express –PCI bridge:

• PCI –E devices can be connected to PCI/PCI-X devices through this bridge.
Layering Overview :
• Packet flow through these 3 different layers.
• Transaction layer
• Data link layer
• Physical layer.
• The Transaction layer is responsible for assembly and de-
assembly TLPs and it is also responsible for credit-based flow.
• The Data link layer provides the link between other 2 layers and
also do error management between the layers. The link layer adds
the sequence number along with the CRC and send it to the
physical layer.
• The Physical layer is collection of physical link , 8b/10b
encoding , interface initialization , scrambling and parallel to
serial conversion .
Layering Overview :
Transaction layer:
• The upper layer of the architecture is the Transaction Layer.
• Transmitter side :
• In transaction layer TLPs are created, These TLPs contains
Header, Data payload and ECRC.
• These TLPs are stored in virtual channels and they are sent to the
Data link Layer through these Virtual channels.
• Before transmitting these TLPs to the receiver side, the transmitter
should get the credits(buffer space) available at the receiver side.
This is referred as credit based flow control.
• Receiver side:
• The receiver stores the packets which are passed from the data
link layer into the virtual channels. If the TD bit is set , it does the
ECRC check and forward the packet to the device core by
removing ECRC.
Address Spaces, Transaction types, and usage:
• Transaction layer supports four address spaces: it includes the
three PCI address spaces (memory , I/O , configuration) and adds
a message space
Address space Address format Description

Memory 32- bit or 64 -bit Used to transfer data from

or to memory mapped
locations.
I/O Only 32 -bit Used to transfer data from
or to I/O locations.
Configuration 32-bit Used to access the
configuration registers.
Messages 64-bit to send or receive
messages from CPU to
endpoint and vice-versa.
POSTED AND NON-POSTED TRANSACTIONS:
TLP PACKET format:
The Transaction Layer packet format is defined as:
• Header is mandatory and it is 3 or 4 DW.
• TLP Digest are optional which contains ECRC (32 bit).
• Payload depends upon the transaction type and it is 1024 DW.
TLP Header(3DW):
1.FORMAT OF THE PACKET:
it tells about the packet format like 3DW ,4DW , with data , without
data.

2.TYPE OF THE PACKET :

it tells about the type of the packet like memory transaction, I/O
transaction, configuration , completion.
 [1:0]

.
3.LENGTH OF THE ASSOCIATED DATA [9:0]: it tells about length of
the data and the payload size supports up to 4096 byte(1024 DW).
4.TRANSACTION DESCRIPTOR: it is a mechanism for carrying
transaction information between the Requester and Completer.it
contains 3 fields:
• Transaction ID - Identifies the outstanding Transactions
• Attributes field – specifies characteristics of the Transaction.
• Traffic Class field –associates Transaction with type of required service.
Transaction ID field:
• The transaction ID consist of two major sub-fields:
• Requester ID
• Tag

• Tag is 8-bit field generated by each Requester, and it must be

unique for all outstanding Requests that require a completion for
that Requester.
• By default, the maximum number of outstanding Requests per
device/function shall be limited to 32, and only the lower 5 bits of
the Tag field are used with the remaining 3 required to be all 0’s
• If the Extended Tag Field Enable bit is set, the maximum is
increased to 256, and the entire Tag field is used .
• The Requester ID field is a 16-bit value that is unique for every
PCI Express function.
• Transaction ID consist of Bus , Device and Function number of
the TLP requester and Tag field of the TLP.
• The routing information fields need this Bus and Device numbers
values.
• These values are captured by the Device and used to generate
the Requester ID field.
Attributes field:
• This field is used to provide additional information that allows
modification of the default handling transactions.
• These modification 2 types
1.Ordering
2.Hardware Coherency management (no snoop)
• Traffic class:
• The Traffic Class (TC) is a 3-bit field that allows differentiation of
transactions into eight traffic classes.
• Traffic class is used to map with virtual channels which present in
transaction layer and is done through the software
5.ADDRESS / ROUTING INFORMATION:
6.BYTE ENABLES:
• First Enable Byte : It is 4 bit field.
• It is active when the Memory , I/O, Configurations is 1DW.
• When the payload size is greater than 1DW then FEB must be active.
• LAST Enable Byte : It is also 4 bit field.
• It is inactive when the Memory , I/O, Configurations is 1DW.
• When the payload size is greater than 1DW then LEB must not be inactive.
COMPLETION STATUS:
All Read Requests and Non-Posted Write Requests require Completion
DATA LINK LAYER:
• It is between Transaction layer and physical layer.
• The main Responsibility of Data link layer is to maintain Data
integrity to detect error and to correct error.
• It also have link initialization and power management responsibility.
• There are 3 types of DLLPs used in managing a link.
1. TLP Acknowledgment ACK / NAK DLLPs.
2. Power Management DLLPs.
3. flow Control Packet DLLPs.
DLLP HEADER FORMAT:

• The DLLP packet size is 8 bytes.

• The 1DW(4bytes) consist of DLLP Type (1byte) and remaining bytes
are vary with DLLP Type.
• The 2DW (4bytes) consist of 16 bit CRC which calculate and added to
Content of in DW.
ACK / NACK PROTOCOL:
• In Transmitter side:
• The Replay buffer stores the TLP with all fields including Data link
layer sequence number and LCRC.
• If we get Ack from the receiver end then LPs which are stored in
replay buffer are removed and if we get NACK from the receiver then
LPs in the buffer are resent to receiver end.
• NEXT_TRANSIT_SEQ_COUNTER:
• It will generate the sequence number to TLP and it is 12 bit counter
counts up to 4095 then it rolls to 0.
• LCRC GENERATOR:
• It generates LCRC to LP to check for CRC error in the receiver end.
• REPLAY_NUM COUNT:
• It is 2 bit counter . It counts how many times does the buffer resent the
LPs.
• REPLAY_TIMER COUNT:
• It is used to measure the time from when TLP is transmitted until an ACK or
NAK DLLP is received.
• ACK_SEQ COUNT:
• It is 12 bit register . It stores most recently received ACK or NAK DLLP.
RECEIVER SIDE:
Receiver buffer : It temporarily stores TLPs in the buffer.
LCRC Check : It checks the received TLPs.
NXT_RCV_SEQ_COUNT: keeps track on the next TLP expected sequence
number.
ACK/NACK DLLP generator : It generates ACK/NACK to transmitter based on
DLLPs.
Physical Layer:
• In Transmitter side:
• The TLPs and DLLPs from Data link layer is sent to physical layer ,
here the start and end bytes are added. If it is a TLP the Start byte is
STP and if the packet is DLLP then the start byte is SDP.
• These Start and End frame are added in transmitter side to know what
is start and end byte for the packet in receiver side.
• In this layer the bits will be encoded by 8b/10b encoding and it
converts the parallel data to serial data.
• In Receiver side:
• It receives the serial bit stream of packets arriving on the differential
lanes, this stream are converted into parallel, then it descrambles and
unstrips the bytes recreating the original packet.
Physical layer:
• There are 2 blocks like logical physical layer and electrical physical
layer.
• LOGICAL SUB BLOCK: It contains multiplexer, byte stripping logic,
scrambling, 8b/10b encoding.
• These framing characters allow the receiver to easily detect start and end of
the packet.
• The framed packet sent to the byte stripping logic 1 byte of the packet is
transferred on 1 lane and the next byte is transferred on the 2nd lane.
• Scrambling: It is the technique which is done to eliminate the repetitive
patterns in the bit stream and provides the synchronization.
• 8b/10b encoding : It maps the 8 bit words to 10 bit symbols to achieve DC
balance.
• The Reverse operation occurs at receiver side of the physical layer like
unstrapping, Descrambling, Decoding, Serial to parallel conversion of data.
• ELECTRICAL SUB BLOCK : The electrical sub block of the physical
layer implemented in embedded logic of FPSC(field programmable system-
on-chip).