Ethernet Specifications and basics:
Key Functions of the MAC Layer
1. Frame Encapsulation / Decapsulation
Transmit (TX): Builds Ethernet frames by adding:
o Preamble (7B) + Start Frame Delimiter (SFD, 1B)
o Destination / Source MAC addresses (6B each)
o EtherType/Length field
o Pad (if payload < 46B)
o Frame Check Sequence (CRC-32, 4B)
Receive (RX): Removes these fields, verifies CRC.
2. Addressing
Uses 48-bit MAC addresses for identification.
Supports:
o Unicast (one-to-one)
o Broadcast (to all devices)
o Multicast (to selected group)
3. Error Detection
Computes CRC-32 during TX, appends it to frame.
On RX, checks CRC to detect errors → drops corrupted frames.
4. Flow Control
Implements IEEE 802.3x pause frames (stop signal to peer).
At higher speeds, also supports Priority-based Flow Control (PFC, IEEE 802.1Qbb) for lossless traffic
(e.g., data center Ethernet).
5. Minimum Frame Size Enforcement
Ensures all frames are at least 64 bytes.
Adds padding if payload is too short.
6. Inter-Packet Gap (IPG) Enforcement
Ensures 96-bit-time gap between frames to allow recovery time for receivers.
7. Half-Duplex (legacy) Media Access
CSMA/CD (Carrier Sense Multiple Access with Collision Detection) in old hub-based Ethernet.
Modern Ethernet is full-duplex switched, so collisions are eliminated, but MAC standard still defines
this behavior.
Functions of PCS (Physical Coding Sublayer)
1. Encoding & Decoding
Maps MAC octets into code-groups that are suitable for transmission over the medium.
Common schemes:
o 8b/10b encoding (used in 1G/10GBASE-X, 1000BASE-X)
o 64b/66b encoding (used in 10GBASE-R, 40G, 100GBASE-R)
o 256b/257b, PAM4 (used in 25G/50G/100G/400G newer standards)
Encoding provides DC balance, enough transitions for clock recovery, and error detection capability.
2. Scrambling / Descrambling
Randomizes the bit pattern to reduce EMI and prevent long runs of 1s/0s.
Helps avoid deterministic interference patterns in high-speed links.
3. Alignment Markers
In multi-lane Ethernet (e.g., 4 × 25G lanes for 100G), the PCS inserts special alignment markers.
These let the receiver deskew and reorder lanes correctly.
4. Lane Distribution and Reassembly
At the transmitter: distributes parallel data across multiple lanes (striping).
At the receiver: collects lanes and reorders them, using alignment markers.
5. Block Synchronization
Detects 64b/66b block boundaries.
Ensures the receiver correctly locks onto the stream structure.
6. Error Detection
Identifies invalid codewords or control characters.
Provides signals to higher layers (MAC) to flag corrupted data.
7. Support for FEC (Forward Error Correction)
PCS often integrates with RS-FEC (Reed-Solomon FEC).
For 25G/100G/400G, FEC is critical to meet BER requirements on challenging channels.
FEC introduces latency but improves link robustness.
Key Functions of PMA
1. Serialization / Deserialization
Converts parallel blocks from PCS into a high-speed serial bitstream for each lane.
On RX, converts serial streams from the medium into parallel data for PCS.
2. Multiplexing / Demultiplexing
For multi-lane Ethernet (e.g., 4×25G = 100G):
o TX: Splits the PCS parallel stream into multiple serialized lanes.
o RX: Combines and re-aligns lanes before passing to PCS.
3. Clock Recovery & Distribution
Works with SerDes to recover the clock from the incoming data stream (CDR).
Provides stable reference clocks for serialization and parallel data exchange.
4. Lane Deskew
Ensures that when multiple lanes arrive with slight timing differences, they are deskewed and
aligned before reassembly.
5. Interface to SerDes (Serializer/Deserializer)
PMA often hosts the SerDes PHY IP.
Provides low-level bit handling, e.g.:
o Gearboxing (changing data widths between PCS and SerDes).
o Bit ordering and polarity correction.
6. Transparent Transport
PMA does not interpret frame content.
It just ensures that the bit-level stream from PCS is faithfully carried over the medium.
Transmit Path (TX)
1. Receives 64b/66b encoded blocks from PCS.
2. Serializes parallel data → serial stream per lane.
3. Distributes bits across multiple lanes.
4. Passes data to PMD/SerDes for electrical/optical conversion.
Receive Path (RX)
1. Accepts high-speed bitstreams from PMD/SerDes.
2. Recovers clock and aligns bits.
3. Deserializes into parallel words.
4. Deskews multiple lanes.
5. Delivers aligned parallel data to PCS.
