Assignment 2: JFET Amplifier Analysis, Stability,
and Applications
Harshit
240141105831018
14/10/2025
1 JFET Amplifiers (Frequency Response)
1.1 The Concept of Frequency Response
A JFET amplifier’s gain isn’t constant across all frequencies. Frequency response analyzes how the
gain (Av ) changes with the input signal frequency. This is crucial for designing amplifiers for specific
applications like audio (20 Hz to 20 kHz) or radio frequencies (MHz range). The response is typically
limited by external capacitors at low frequencies and internal device capacitances at high frequencies.
1.2 Low-Frequency Response
The low-frequency response is primarily determined by the coupling capacitors (CC ) and bypass
capacitors (CS ).
• Coupling Capacitors: These block DC current from flowing between stages or to the load but
allow the AC signal to pass. At very low frequencies, their reactance (XC = 1/(2πf C)) becomes
large, forming a voltage divider with the input resistance and causing the gain to ”roll-off” or
decrease.
• Bypass Capacitors: A source bypass capacitor (CS ) is used to short the source resistor (RS )
for AC signals, preventing gain reduction. At low frequencies, its reactance increases, making the
bypass less effective and reducing the overall voltage gain.
The lower cutoff frequency (fL ) is the point where the gain drops by 3 dB (to 70.7% of its
mid-band value).
2 Biasing the JFET (Stability and Load Line Analysis)
2.1 Q-Point Stability
The goal of biasing is to establish a stable DC operating point (Q-point), defined by (IDQ , VGSQ ).
However, JFET parameters like IDSS and VP vary significantly with temperature and between devices
of the same type. Stability refers to how well the biasing circuit maintains a constant Q-point despite
these variations. A stable design ensures predictable performance. Voltage-divider bias offers excellent
stability due to its independence from device parameter variations.
1
2.2 DC Load Line Analysis
A DC load line is a graphical tool used to visualize the possible DC operating points of the JFET. It’s
a line drawn on the JFET’s characteristic curves (ID vs. VDS ) that represents all possible combinations
of ID and VDS for a given circuit.
The equation for the load line is derived from Kirchhoff’s Voltage Law in the drain-source loop:
VDS = VDD − ID (RD + RS )
The Q-point is the intersection of this load line and the characteristic curve corresponding to the specific
bias voltage VGSQ .
2.3 Example: Voltage-Divider Bias Design
Let’s design a stable biasing circuit.
Given: VDD = 15 V, IDSS = 10 mA, VP = −4 V.
Target Q-Point: IDQ = 4 mA, VDSQ = 7 V.
1. Find VGSQ :
Using the Shockley equation:
2
VGSQ
IDQ = IDSS 1 −
VP
2
√
VGSQ VGSQ
4 = 10 1 − =⇒ 0.4 = 1 +
−4 4
VGSQ
0.632 = 1 + =⇒ VGSQ = −1.47 V
4
2. Find RS :
The source voltage is VS = VG − VGSQ . Let’s set the gate voltage VG = 1 V for good stability.
VS = 1 V − (−1.47 V) = 2.47 V
VS 2.47 V
RS = = = 617.5 Ω ≈ 620 Ω
IDQ 4 mA
3. Find RD :
VDD − VDSQ − VS 15 V − 7 V − 2.47 V 5.53 V
RD = = = = 1382.5 Ω ≈ 1.3 kΩ
IDQ 4 mA 4 mA
4. Find R1 and R2 :
To set VG = 1 V, we use the voltage divider rule. Choose a large R2 = 1 MΩ for high input
impedance.
R2 1 MΩ
VG = VDD =⇒ 1 V = 15 V
R1 + R2 R1 + 1 MΩ
R1 + 1 MΩ = 15 MΩ =⇒ R1 = 14 MΩ
3 FET as a Voltage Variable Resistor (VVR): High-Frequency
Effects
3.1 High-Frequency Model and Miller Effect
At high frequencies, the JFET’s internal parasitic capacitances (Cgs , Cgd , and Cds ) can no longer be
ignored. These capacitances exist between the device terminals.
2
The most critical of these is the gate-drain capacitance, Cgd , due to the Miller Effect. In a common-
source amplifier, this capacitance appears amplified at the input. The effective input capacitance is given
by:
Cin(M iller) = Cgs + Cgd (1 − Av )
Since the voltage gain Av is large and negative for a CS amplifier, the term (1 − Av ) becomes very large,
significantly increasing the input capacitance. This large capacitance shunts the input signal to ground
at high frequencies, causing the gain to roll-off.
3.2 Upper Cutoff Frequency
The upper cutoff frequency (fH ) is determined by this Miller capacitance and the equivalent resistance
at the input port. This effect limits the useful bandwidth of the amplifier. The common-gate and
common-drain (source follower) configurations are less susceptible to the Miller effect and are therefore
preferred for high-frequency applications.
4 Key Points for Revision
• Amplifier gain is not infinite; it’s limited by frequency response. Low frequencies are affected
by external capacitors, while high frequencies are limited by internal device capacitances.
• The Miller Effect in common-source amplifiers dramatically increases input capacitance, limiting
high-frequency performance.
• Biasing must ensure a stable Q-point against temperature changes and device variations. Voltage-
divider bias is superior in this regard.
• The DC Load Line is a powerful graphical method to determine the exact operating point of the
transistor in a specific circuit configuration.
