Chapter #8: Finite State Machine Design

Chapter #8: Finite State Machine Design
No. 8-1
Motivation
Counters: Sequential Circuits where State = Output
Generalizes to Finite State Machines:
Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic
Application of Sequential Logic Design Techniques
Word Problems
Mapping into formal representations of FSM behavior
Case Studies
No. 8-2
Chapter Overview
Concept of the State Machine
Partitioning into Datapath and Control
When Inputs are Sampled and Outputs Asserted
Basic Design Approach
Six Step Design Process
Alternative State Machine Representations
State Diagram, ASM Notation, VHDL, ABEL Description Language
Moore and Mealy Machines
Definitions, Implementation Examples
Word Problems
Case Studies
No. 8-3
Concept of the State

Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset
0
Even
[0]
1
1
Odd
[1]
State
Diagram
Present State
Even
Even
Odd
Odd
Input
0
1
0
1
Next State
Even
Odd
Odd
Even
Output
0
0
1
1
Symbolic State Transition Table

Present State
0
0
1
1
Input
0
1
0
1
Next State
0
1
1
0
Output
0
0
1
1
Encoded State Transition Table
No. 8-5

Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
Input
NS
Input
CLK
Q
R
CLK
PS/Output
\Reset
T FF Implementation
D FF Implementation
1
Output
Q
R
\Reset
Input
Clk
Output
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

No. 8-6
Concept of State
Machine
Timing:
When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
Clocking event causes state/outputs to transition, based on inputs
For set-up/hold time considerations:
Inputs should be stable before clocking event
After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event
No. 8-7
Concept of State
Machine
Example: Positive Edge Triggered Synchronous System
State T ime
Clock
On rising edge, inputs sampled

outputs, next state computed
After propagation delay, outputs and
next state become stable
Inputs
Immediate Outputs:
affect datapath immediately
could cause inputs from datapath to change
Outputs
Delayed Outputs:
take effect on next clock edge
propagation delays must exceed hold times
No. 8-8

Machine
Communicating State Machines
One machine's output is another machine's input
X
CLK
FSM 2
FSM 1
Y
FSM 1
A
[1]
Y=0
Y=0
X=0
X=0
FSM 2
C
[0]
X=1
Y=1
X=1
Y=0,1
B
[0]
X=0
D
[1]
Fragment state diagrams

Initial inputs/outputs: X = 0, Y = 0
No. 8-9

Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment (or encoding)
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3~6 covered later (Chap. 9);
5 and 6 generalized from the counter design procedure
No. 8-10

Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes (10 cents), nickels (5 cents)
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor D
Re se t
Ve nding
M achine
FSM
Ope n
Gum
Release
M echanism
Clk
No. 8-11
Vending Machine Example

Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Reset
S0
N
Draw state diagram:

S1
Inputs: N, D, reset
Output: open
S2
S4
S5
S6
[open]
[open]
[open]
S3
S7
S8
[open]
[open]
No. 8-12

Step 3: State Minimization
Present
State
Reset
0
0
N
5
D
N
10
D
N, D
10
15
[open]
15
reuse states
whenever
possible
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0
5
10
X
5
10
15
X
10
15
15
X
15
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
No. 8-13

Step 4: State Encoding
Present State
Q1 Q0
0
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
No. 8-14
Parity Checker Example

Step 5. Choose FFs for implementation
D FF easiest to use
D1
Q1
D
Q0
N
N
\ Q0
Q0
\N
Q1
N
Q1
D
D0
D1 D
CLK
Q1
RQ
\ Q1
D1 = Q1 + D + Q0 N
\reset
OPEN
D0 D
CLK
Open
Q0
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
\ Q0
RQ
\reset
8 Gates
No. 8-15
Parity Checker Example

Step 5. Choosing FF for Implementation
J-K FF
Present State
Q1 Q0
0
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
J1
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table

No. 8-16

Implementation:
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
N
Q0
D
\ Q0
J
CLK
K RQ
Q1
\ Q1
OPEN
Q1
D
CLK
\ Q1
KR Q
N
\reset
Q0
\ Q0
7 Gates
No. 8-17

Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified
sequence of actions based on input data
algorithm = sequencing + data manipulation
separation of control and data
Gradual shift towards program-like representations:

Algorithmic State Machine (ASM) Notation
Hardware Description Languages (e.g., VHDL)
No. 8-18

Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
State Box
Decision Box
Output Box
State Machine in one state
block per state time
Single Entry Point
Unambiguous Exit Path
for each combination
of inputs
Outputs asserted high (.H)
or low (.L); Immediate (I)
or delayed til next clock
State
Entry Path
State Code
*
State
Name
State
Output List
T
***
State Box
Condition
Condition
Box
Conditional
Output List
ASM
Block
Output
Box
Exits to
other ASM Blocks
No. 8-19

ASM Notation
Condition Boxes:
Ordering has no effect on final outcome
Equivalent ASM charts:
A exits to B on (I0 & I1 = 1) else exit to C
A
010
I0
T
010
I1
T
F
I1
F
F
I0
T
B
C
No. 8-20

Example: Parity Checker
Input X, Output Z
Even
Nothing in output list implies Z not asserted

Z asserted in State Odd
F
X
T
Odd
1
H.Z
Trace
Tracepaths
pathsto
toderive
derive
state
transition
state transitiontables
tables
Symbolic State Table:

Present Next
Input State
State Output
F
Even
Even
T
Even
Odd
F
A
Odd
Odd
T
A
Odd
Even
Encoded State Table:
Present Next
Input State
State Output
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
0
No. 8-21

ASM Chart for Vending Machine
00
10
10
F
F
F
F
15
01
11
H.Open
N
F
F
Reset
T
T
0
No. 8-22
Moore and Mealy Machine Design Procedure

Definitions
State
Register
Xi
Inputs
Moore Machine
Comb.
Logic for
Outputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Zk
Outputs
Clock
Outputs are function

solely of the current
state
Outputs change
synchronously with
state changes
state
feedback
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
State
Feedback
Mealy Machine
Outputs depend on
state AND inputs
Input change causes
an immediate output
change
Asynchronous outputs
No. 8-23

State Diagram Equivalents
Moore
Machine
N D + Reset
Reset
(N D + Reset)/0
Reset/0
Mealy
Machine
[0]
Reset
Reset/0
N/0
5
ND
[0]
5
D
N D/0
N/0
10
D
D/0
[0]
10
ND
N+D
D/1
N D/0
N+D/1
15
[1]
15
Reset
Outputs are associated

with State
Reset/1
Outputs are associated

with Transitions
No. 8-24

States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
Asserts its output

whenever at least two
1s in sequence
0/0
0
[0]
0
Same I/O behavior
1
1/1
[0]
Different # of states
1/0
0/0
1
2
[1]
S0
00
IN
S1
S0
01
IN
S2 T
10
H.OUT
IN
IN
S1
IN
Equivalent
ASM Charts
T
H.OUT
T
No. 8-25

Timing Behavior of Moore Machines
Reverse engineer the following: why Moore ???
X
X
\B
J
Q
C
KR Q
FFa
A
\A
Input X
Output Z
State A, B (= Z)
\Reset
Clk
X
X
\A
J
Q
C
KR Q
FFb
Z
\B
\Reset
Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table
Formal: Derive next state/output functions by analyzing the circuit
No. 8-26

Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
100
X
Clk
A
Z
\Reset
Reset
X=1
X=0
X=1
X= 0
X=1
X= 0
X= 0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B
0 0
Partially Derived
State Transition
Table
0 1
1 0
1 1
X
0
1
0
1
0
1
0
1
A+
?
1
0
?
1
0
1
1
B+
?
1
0
?
0
1
1
0
Z
0
0
1
1
0
0
1
1
No. 8-27

Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!
Ja = X
Jb = X
Ka = X B
Kb = X xor A
Z=B
FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q

A+ = Ja A + Ka A = X A + (X + B) A
B+ = Jb B + Kb B = X B + (X A + X A) B
Next State K-Maps:
State 00, Input 0 State 00

State 01, Input 1 State 11
No. 8-28

Complete ASM Chart for the Mystery Moore Machine
00
S0
11
S3
H.Z
X
1
S1
01
S2
10
H.Z
0
Note: All Outputs Associated With State Boxes

No Separate Output Boxes, Intrinsic in Moore Machines
No. 8-29

Reverse Engineering a Mealy Machine
Clk
DA
D
C
Q
R Q
\A
X
\A
\X
J
Q
C
KR Q
\Reset
A
X
B
\B
\Reset
DA
\X
B
Z
\X
X
A
Input X, Output Z, State A, B

State register consists of D FF and J-K FF
No. 8-30
Moore and Mealy Machine

Ad Hoc Method
Signal Trace of Input Sequence 101011:
100
Note glitches
in Z!
Clk
A
Outputs valid at
following falling
clock edge
B
Z
\Reset
Reset
AB =00
Z =0
X =1
AB =00
Z =0
X =0
AB =00
Z =0
X =1
AB =01
Z =0
X =0
AB =11
Z=1
A B
0 0
Partially completed
state transition table
based on the signal
trace
0 1
1 0
1 1
X
0
1
0
1
0
1
0
1
X =1
AB =10
Z =1
A+
0
0
?
1
?
0
1
?
X =1
AB =01
Z =0
B+
1
0
?
1
?
1
0
?
Z
0
0
?
0
?
1
1
?
No. 8-31

Formal Method
A+ = B (A + X) = A B + B X
B+ = Jb B + Kb B = (A xor X) B + X B
= AB X + AB X + B X
Z
= AX + B X
A+
Missing Transitions and Outputs:

State 01, Input 0 -> State 00, Output 1
B+
Z
No. 8-32

ASM Chart for Mystery Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11
S0
H. Z
00
0
X
0
S1
10
S2
H. Z
X
1
S3
01
11
H.Z
X
0
NOTE: Some Outputs in Output Boxes as well as State Boxes

This is intrinsic in Mealy Machine implementation
No. 8-33

Synchronous Mealy Machine
Clock
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
state
feedback
latched state AND outputs

avoids glitchy outputs!
No. 8-34
Finite State Machine Word Problems

Mapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
We will use state diagrams and ASM Charts
No. 8-35

Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence 010
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010
Z: 00010101000
X: 11011010010
Z: 00000001000
No. 8-36

Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
Moore State Diagram

Reset signal places
FSM in S0
Outputs 1
Loops in State
No. 8-37

Exit conditions from state S3:
if next input is 0 then have 0100 (state S6)
if next input is 1 then have 0101 (state S2)
No. 8-38

Exit conditions from S1: recognizes strings of form 0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form 1 (no 0 seen)
loop back to S4 if input is 1
No. 8-39

S2, S5 with incomplete transitions
S2 = 01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = 10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram
No. 8-40

Review of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences
to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions
like the specification
No. 8-41

Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)

001
010
110
111
101
110
111
No. 8-42

Complex Counter
One state for each output combination
Add appropriate arcs for the mode control
S0
S1
S2
000
001
H.Z 0
1
010
H.Z 1
S3
011
H.Z 1
H.Z 0
0
1
1
S6
110
S4
H.Z 2
H.Z 1
S7
111
H.Z 2
H.Z 1
H.Z 0
0
100
H.Z 2
0
S5
101
H.Z 2
H.Z 0
1
0
No. 8-43

A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
No. 8-44

Picture of Highway/Farmroad Intersection:
Farmroad
C
HL
FL
Highway
Highway
HL
FL
C
Farmroad
No. 8-45

Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others

State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
No. 8-46

Refinement of ASM Chart:
Start with basic sequencing and outputs:
S0
S3
H.HG
H.FR
H.HR
H.FY
S1
H.HY
H.FR
S2
H.HR
H.FG
No. 8-47

Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C TL
S0
S0
H.HG
H.FR
0
H.HG
H.FR
0
TL
C TL
TL C
1
0
1
H.ST
1
H.ST
S1
H.HY
H.FR
S1
H.HY
H.FR
Equivalent ASM Chart Fragments

No. 8-48

S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
S1
H.HY
H.FR
0
TS
H.ST
S2
H.HR
H.FG
No. 8-49

S2 Exit Condition: no car waiting OR long time interval expired
S0
H.HG
H.FR
0
H.ST
1
TL C
S3
H.HR
H.FY
TS
1
H.ST
S1
H.HY
H.FR
0
TS
H.ST
H.ST
S2
H.HR
H.FG
0
TL + C
1
Complete ASM Chart for Traffic Light Controller

No. 8-50

Compare with state diagram:
TL + C
Reset
S0
TLC/ST
TS/ST
S1: HY
TS
S1
S2: FG
S3
TS
TS/ST
S2
S0: HG
S3: FY
TL + C/ST
TL C
Advantages of ASM Charts:

Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand the design as an algorithm
No. 8-51

"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination
No. 8-52

Understanding the problem: draw a block diagram
RESET
Operator Data
ENTER
UNLOCK
KEY-IN
Combination
Lock FSM
Internal
Combination
Inputs:
Reset
Enter
Key-In
L0, L1, L2
ERROR
L0
L1
L2
Outputs:
Unlock
Error
No. 8-53

Enumeration of states:
what sequences lead to opening the door?
error conditions on a second pass
START state plus three key COMParison states
START
START entered on RESET

Exit START when ENTER is pressed
1
Reset
0
Enter
COMP0
KI = L0
Continue on if Key-In matches L0
Y
No. 8-54

COMP0
IDLE1
Path to unlock:
KI = L 0
COMP2
IDLE0
Enter
Wait for
Enter Key press
Enter
COMP1
KI = L2
DONE
H.Unlock
Compare Key-IN
KI = L1
Y
Reset
1
START
No. 8-55

Now consider error paths
Should follow a similar sequence as UNLOCK path, except
asserting ERROR at the end:
IDLE0'
ERROR3
IDLE1'
H.Error
0
Enter
ERROR1
Enter
ERROR2
Reset
START
COMP0 error exits to IDLE0'

COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
No. 8-56

Reset + Enter
Reset
Start
Reset Enter
Com p0
KI = L0
KI L0
Enter
Enter
Idle0
Idle0'
Enter
Equivalent State Diagram
Enter
Com p1
KI = L1
Enter
Error1
KI L1
Enter
Idle1
Idle1'
Enter
Enter
Com p2
KI = L2
Reset
Done
[Unlock]
Reset
Start
Error2
KI L2
Error3
[Error]
Reset
Reset
Start
No. 8-57
Chapter Review
Basic Timing Behavior an FSM
when are inputs sampled, next state/outputs transition and stabilize
Moore and Mealy (Async and Sync) machine organizations
outputs = F(state) vs. outputs = F(state, inputs)
First Two Steps of the Six Step Procedure for FSM Design
understanding the problem
abstract representation of the FSM
Abstract Representations of an FSM
ASM Charts
Word Problems
understand I/O behavior; draw diagrams
enumerate states for the "goal"; expand with error conditions
reuse states whenever possible
No. 8-58

Chapter #8: Finite State Machine Design

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Chapter #8: Finite State Machine Design

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Chapter #8: Finite State Machine Design

Concept of the State

Symbolic State Transition Table

Encoded State Transition Table

Concept of the State

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

On rising edge, inputs sampled

Concept of the State

Fragment state diagrams

Basic Design Approach

Basic Design Approach

Vending Machine Example

Draw state diagram:

Vending Machine Example

Symbolic State Table

Vending Machine Example

Parity Checker Example

Parity Checker Example

Remapped encoded state transition table

Vending Machine Example

Alternative State Machine Representations

Gradual shift towards program-like representations:

Alternative State Machine Representations

Alternative State Machine Representations

Alternative State Machine Representations

Nothing in output list implies Z not asserted

Symbolic State Table:

Alternative State Machine Representations

Moore and Mealy Machine Design Procedure

Outputs are function

Moore and Mealy Machines

Outputs are associated

Outputs are associated

Moore and Mealy Machines

Asserts its output

Same I/O behavior

Moore and Mealy Machines

Two Techniques for Reverse Engineering:

Moore and Mealy Machines

Moore and Mealy Machines

FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q

State 00, Input 0 State 00

Moore and Mealy Machines

Note: All Outputs Associated With State Boxes

Moore and Mealy Machines

Input X, Output Z, State A, B

Moore and Mealy Machine

Moore and Mealy Machines

Missing Transitions and Outputs:

Moore and Mealy Machines

NOTE: Some Outputs in Output Boxes as well as State Boxes

Moore and Mealy Machines

latched state AND outputs

Finite State Machine Word Problems

Finite State Machine Word Problems

Finite State Machine Word Problems

Moore State Diagram

Finite State Machine Word Problems

Finite State Machine Word Problems

Finite State Machine Word Problems

Final State Diagram

Finite State Machine Word Problems