MEMORY SEGMENTATION

IN 80386
Naman Dora
C009
Rohin Joshi

Memory of 80386
The

memory of 80386 consists of 3 modes :-

1.

Real address mode : In this mode 80386

appears 8086 with some new instructions.

2.

Protected mode : It is mainly used for

multitasking operations .

3.

Virtual mode: Its a dynamic mode which

switches to protected mode when a 80386
instruction is to be executed and back to the
virtual mode when an 8086 function is to be
executed .

Memory segmentation in Real

mode:
80386

can access only 4 segments at a time

i.e. code segment ,data segment ,stack
segment and extra segment in real and virtual
mode.

To

access these four segments 80386 has four

16-bit segment registers CS,DS,SS,ES.

They

are used to hold the base address and 16

bit offset registers to hold the offset address
for each of the segment.

Code segment
Programs

are stored In this segment

Instruction

fetch operation is performed

from code segment.

Cs

register holds 16 bit base address

and IP register holds 16 bit offset
address

Data segment
Data

is stored In this segment

This

also holds Source operands during

string operations.

Ds

register holds 16 bit base address

and BX register holds 16 bit offset
address.

SI

register holds 16 bit offset address

during string operation.

Stack segment
This

segment holds the stack which

operates in LIFO manner.

Stack

segment holds its base address

and SP holds 16 bit offset address of the
top of the stack .

Base

pointer is used as an offset register

during random access of stack .

Extra segment
Mainly

stores destination operands

during string operations .

ES

holds the base address and BI holds

the offset address during string
operations.

Segmentation in Protected
Mode :
The

segment size in the protection mode

for 80386 can be anything between 1
byte to 4 GB .

Also,

the segment base address can

start from anywhere removing the
constraint which was their in 8086.

 Hence

the entire memory is accessible in

protection mode also the memory
beyond 1 MB.

The

logical address in protected mode

architecture is formed out of two
components :-

1.

The 16 bit selector and the

2.

32 bit offset

A paging unit has been added as a

second layer of address translation
between the segmentation unit and the
physical bus.

The

paging unit may be enabled or

disabled; if disabled, operation is the
same as on the 80286. If the paging unit
is enabled, addresses in a segment are
now virtual addresses, rather than
physical addresses as they were on the
80286.

The segment starting address, the

offset, and the final 32-bit address the
segmentation unit derived by adding the
two are all virtual (or logical) addresses
when the paging unit is enabled.

When the segmentation unit generates

and validates these 32-bit virtual
addresses, the enabled paging unit
finally translates these virtual addresses
into physical addresses.

Bibliography

https://en.wikipedia.org/wiki/Intel_80386

http://www.csee.umbc.edu/~
cpatel2/links/310/slides/chap17_lect16_paging_segmentation.pdf

Harish G Narula : Microprocessors for computer engineering.

THANK YOU