Unit-3 8085 Microprocessor: Prof. Swati Sharma

Unit-3
8085 Microprocessor
Prof. Swati Sharma
swati.sharma@darshan.ac.in
Microprocessor
Unit-3
Unit-3 8085
8085 Microprocessor
Microprocessor && Interfacing
Microprocessor 2150707 1
Interfacing -- 2150707 Darshan
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Subject Overview
Sr. No. Unit % Weightage
1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 10%
4 Assembly Language Programming Basics 10%
5 8085 Assembly Language Programs 10%
6 Stack & Subroutines 10%
7 I/O Interfacing 15%
8 Advanced Microprocessors 20%
9 SUN SPARC Microprocessor 5%
10 ARM Processor 5%
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Unit-3 8085
8085 Microprocessor
Microprocessor 2 Darshan
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8085 Architecture
3
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Unit-3 8085
8085 Microprocessor
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8085 Architecture
8085 is pronounced as "eighty-eighty-five" microprocessor.
It is an 8-bit microprocessor designed by Intel in 1977 using NMOS
technology.
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8085 Microprocessor
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Introduction to 8085
8 bit General purpose microprocessor (i.e. 8-bit data bus)
It is as single chip N MOS device with 40 pins
It has multiplexed address and data bus.(AD0-AD7).
It works on 5-Volt dc power supply.
The maximum clock frequency is 3-MHz while minimum frequency
is 500-kHz.
It provides 74 instructions with 5 different addressing mode.
It provides 16 address lines. Therefore, capable of addredding 2 16=
64K of memory.
It supports external interrupt request.
A 16 bit program counters (PC)
A 16 bit stack pointer (SP)
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8085 Microprocessor
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Introduction to 8085
It generates 8 bit I/O address so it can access 28=256 input ports.
It provides 5 hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5,
INTR.
It provides Accumulator, flag register, 6 general purpose registers
and two special purpose registers (SP,PC).
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Unit-3 8085
8085 Microprocessor
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8085 Programming Model
7
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Unit-3 8085
8085 Microprocessor
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Accumulator A (8) Flag Register
B (8) C (8)
D (8) E (8)
H (8) L (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
Data Bus Address Bus
16
8 Lines
Lines
Bidirectional Unidirectional
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Unit-3 8085
8085 Microprocessor
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Registers
Accumulator
Flags
Program Counter
Stack Pointer
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Unit-3 8085
8085 Microprocessor
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General Purpose Registers

B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8 Lines
Lines
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8085 Microprocessor
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Registers
6 general purpose registers to store 8-bit data
B, C, D, E, H & L.
Can be combined as register pairs BC, DE, HL to perform
16-bit operations.
Used to store or copy data using data copy instructions.
General purpose registers
B (8) C (8)
D (8) E (8)
H (8) L (8)
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8085 Microprocessor
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8 Lines
Lines
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8085 Microprocessor
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Accumulator
8 - bit register, identified as A
Part of ALU
Used to store 8-bit data to perform arithmetic & logical
operations.
Result of operation is stored in it.
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8 Lines
Lines
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Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
P -Parity Flag
Set to 1 if result has even no. of 1s
S -Sign Flag & Reset if result has odd no. of 1s
Set to 1 if bit D7 of result is 1;
AC -Auxiliary
1 0 0 Carry
1 0 0Flag
1 1 CY -Carry Flag
otherwise reset
1 0 1 0 1 0 1 0 Set to 1Pwhen
= 1 carry bit is Set to 1 if arithmetic
Z -Zero Flag S = 1 generated by bit D3 & operation results in
Set to 1 when result is zero; passed to bit D4 carry;
otherwise reset otherwise reset
1 1 1 1 1 1
1 0 1 0 0 0 1 0 11001100 1 0 1 0
-1 0 1 0 + 0 1 1 0+ 10010110 1 0 0 1
0 0 0 0 1 0 0 11 00001011 0 0 1 1
Z=1 AC = 1 CY = 1
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Flag Register
ALU has 5 Flag Register that set-reset after an operation according
to data conditions of the result in accumulator & other registers.
Helpful in decision making process of P
Conditions are tested through software instructions
For e.g.
JC (Jump On Carry) is implemented to change the sequence of
program when CY is set.
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8 Lines
Lines
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Program Counter & Stack Pointer
16-bit registers used to hold memory addresses.
Size is 16-bits because memory addresses are 16-bits.
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8 Lines
Lines
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8085 Microprocessor
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Program Counter (PC)
P uses PC register to sequence the execution of instructions.
Its function is to point to memory address from which next byte is

to be fetched.
When a byte is being fetched, PC is incremented by 1 to point to
next memory location.
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Stack Pointer
Used as memory pointer
Points to the memory location in R/W memory, called Stack.
Beginning of stack is defined by loading a 16-bit address in the

stack pointer.
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8085 Microprocessor
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Bus Organization of 8085
22
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A15
Address Bus
A0
Memory Input
8085 MPU Output Real

World
D7
Data Bus
D0
Control Bus
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Address Bus
Group of 16 lines generally identified as A0 to A15.
It is unidirectional
i.e. bits flow from microprocessor to peripheral devices.
16 address lines are capable of addressing 65536 memory
locations.
So, 8085 has 64K memory locations.
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A15
Address Bus
A0
Memory Input

World
D7
Data Bus
D0
Control Bus
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Data Bus
Group of 8 lines identified as D0 to D7.
They are bidirectional i.e. data flow in both directions between

microprocessor, memory & peripheral.
8 data lines enable microprocessor to manipulate data ranging
from 00H to FFH (28=256 numbers).
Largest number appear on data bus is 1111 1111 => (255)10.
As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.
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A15
Address Bus
A0
Memory Input

World
D7
Data Bus
D0
Control Bus
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Control Bus
It comprises of various single lines that carry synchronization,
timing & control signals.
These signals are used to identify a devise type with which MPU
intends to communicate.
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8085 Pin Diagram X1 1 40 Vcc
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST 7.5 7 34 IO/M
RST 6.5 8 33 S1
RST 5.5 9 32 RD
INTR 10 31 WR
8085A
INTA 11 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
Vss 20 21 A8 29
8085 Pin Diagram
8-bit general purpose microprocessor
Capable of addressing 64K of memory
It has 40 pins
Requires +5V single power supply
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8085 Pin Diagram
All signals can be classified into six groups:
i. Address Bus
ii. Data Bus
iii. Control & Status Signals
iv. Power Supply & Frequency signals
v. Externally initiated signals
vi. Serial I/O Ports
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8085 Pin Diagram
(i) Address Bus
16 signal lines are used as
address bus.
However these lines are split into
two segments:
A15 - A8 and AD7 - AD0
A15 - A8 are unidirectional and are
used to carry high-order address
of 16-bit address.
AD7 - AD0 are used for dual
purpose.
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8085 Pin Diagram
(ii) Multiplexed Address/Data Bus
Signal lines AD7-AD0 are
bidirectional and serve dual
purpose.
They are used as low-order address
bus as well as data bus.
The low order address bus can be
separate from these signals by
using a latch.
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8085 Pin Diagram
(iii) Control & Status Signals
To identify nature of operation
Two Control Signals
i. RD(Read)
ii. WR(Write)
Three Status Signals
i. S1
ii. S0
iii. IO/M
To indicate beginning of operation
One Special Signal called ALE(Address
Latch Enable)
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8085 Pin Diagram
ALE: Pin 30
This is positive going pulse
generated every time the 8085
begins an operation (machine cycle)
It indicates that the bits on AD7-AD0
are address bits
This signal is used primarily to latch
the low-address from multiplexed
bus & generate a separate set of
address lines A7-A0.
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8085 Pin Diagram
(iii)Control & Status Signals
RD(Read): Pin 32
This is a read control signal (active
low)
This signal indicates that the
selected I/O or Memory device is
to be read & data are available on
data bus.
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8085 Pin Diagram
IO/M: Pin 34
This is a status signal used to
differentiate I/O and memory
operation
When it is high, it indicates an I/O
operation
When it is low, it indicates a memory
operation
This signal is combined with RD and
WR to generate I/O & memory
control signals
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8085 Pin Diagram
(iii)Control & Status Signals
S1 & S0: Pin 29, 33
These status signals can identify
various operations, but they are
rarely used in small systems.
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODE
FETCH
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8085 Pin Diagram
Machine Cycle IO/M S1 S0 Control Signals
Opcode Fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I/O Read 1 1 0 RD = 0
I/O Write 1 0 1 WR = 0
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8085 Pin Diagram
(iv) Power Supply & Frequency
Signal
VccPin no. 40, +5V Supply
Vss Pin no.20, Ground
Reference
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8085 Pin Diagram
(iv)Power Supply & Frequency Signal
X1, X2 Pin no.1 & 2, Crystal
Oscillator is connected at these
two pins.
The frequency is internally divided
by two;
therefore, to operate a system at
3MHz, the crystal should have a
frequency of 6MHz.
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8085 Pin Diagram
(iv)Power Supply & Frequency Signal
CLK (OUT) Clock output
Pin No.37: This signal can be used

as the system clock for other
devices.
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8085 Pin Diagram
(v) Externally Initiated Signals
including Interrupts
INTR(Input) Interrupt Request
It is used as general purpose
interrupt
INTA(Output) Interrupt
Acknowledge.
It is used to acknowledge an
interrupt.
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8085 Pin Diagram
RST7.5, RST6.5, RST5.5 (Input)
Restart Interrupts.
These are vector interrupts that
transfer the program control to
specific memory locations.
They have higher priorities than
INTR interrupt.
Among these 3 interrupts, the
priority order is RST7.5, RST6.5,
RST5.5
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8085 Pin Diagram
TRAP(Input) This is a non
maskable interrupt & has the
highest priority.
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8085 Pin Diagram
HOLD(Input) This signal
indicates that a peripheral such as
DMA Controller is requesting the
use of address & data buses
HLDA(Output) Hold
Acknowledge. This signal
acknowledges the HOLD request
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8085 Pin Diagram
READY(Input) This signal is used
to delay the microprocessor read or
write cycles until as low-responding
peripheral is ready to send or accept
data.
When the signal goes low, the
microprocessor waits for an integral
no. of clock cycles until it goes high.
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8085 Pin Diagram
RESET IN (Input) When the
signal on this pin goes low, the
Program Counter is set to zero,
the buses are tri-stated &
microprocessor is reset.
RESET OUT (Output) This signal
indicates that microprocessor is
being reset. The signal can be
used to reset other devices.
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8085 Pin Diagram
(vi) Serial I/O Ports
Two pins for serial transmission
i. SID (Serial Input Data)
ii. SOD (Serial Output Data)
In serial transmission, data bits
are sent over a single line, one bit
at a time.
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8085 Microprocessor Signals GND
+5 V
5 1 2 40 20
Serial SID
SOD 4 28
I/O
Ports High-Order
Address Bus
TRAP 6 21
RST 7.5 7
RST 6.5 8
RST 5.5 9
Externally INTR 10 19
Initiated Multiplexed
Signals
READY 35 8085A Address/Data Busi
HOLD 39 12
RESET IN 36 30
29 ALE
External Signal INTA 11
HLDA 33
38 Control and
Acknowledgement 34
32 IO/M Status Signals
31 RD
WR
3 37
RESET CLK
OUT OUT 50
8085 Architecture/Block Diagram
51
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INTA RST 6.5 TRAP
INTR RST 5.5 RST 7.5 SID SOD
Interrupt Control Serial I/O Control

8-Bit Internal Data
Bus
Instructio
Accumulator (8) Temp. Reg. (8) Multiplexer
n Reg. (8)
W (8) Z (8)
Flag (5) Temp. Reg. Temp. Reg.
Flip-Flops Instruction B (8) C (8)
Decoder Reg. Reg.
and D (8) E (8)
Arithmetic Machine Reg. Reg.
Reg. Select
Logic Unit Cycle Register
(ALU) (8) H (8) L (8)
Encoding Reg. Reg. Array
Stack Pointer (16)
Power +5 V Program Counter (16)

Supply Increment/Decrement
GND
Address Latch (16)
X1 CLK Timing and Control Reset
X2 GEN Control Status DMA
Address Buffer Data/Address Buffer
(8) (8)
CLK RD ALE S0 S1 IO/M HLDA RESET OUT
OUT WR HOLD RESET IN A15 - A8
READY A7 - A1
Address Address/Data
52
Bus Bus
INTA RST 6.5 TRAP

8-Bit Internal Data
Bus
Instructio
n Reg. (8)
W (8) Z (8)
Decoder Reg. Reg.
and D (8) E (8)
Reg. Select
(ALU) (8) H (8) L (8)
Stack Pointer (16)

GND
Address Latch (16)
(8) (8)
READY A7 - A1
53
Bus Bus
INTA RST 6.5 TRAP
Used toINTR
hold data (i.e.RST
RST 5.5 temporary
7.5 SID SOD
data) duringInterrupt
ALU operation.
Control Serial I/O Control
8-Bit Internal Data
Bus When Instruction is fetched from
Accumulator (8) Temp. Reg. (8) Instructio memory, it is loaded in the
Multiplexer
n Reg. (8) Instruction
W (8)
Registor
Z (8)
(IR).
Flag (5)
Flip-Flops S Z Reg. AC
Temp. Temp. Reg. P CY
Instruction B (8) C (8)
Decoder Reg. Reg.
Arithmetic
and Instruction
D (8) decoder
E (8) decodes
Machine Reg.
theReg.
information presentRegister
in the
Reg. Select
Logic Unit Cycle
(ALU) (8) H (8) L (8)
Encoding Instruction
Reg. register.
Reg. Array
Stack Pointer (16)

GND
Performs
Used to store Computing
8-bit data toFuctions
perform arithmetic & logical
Address Latch (16)
X1 CLK Timing and Control
Accumulator, Temporary Reset
Xoperations.
GEN Control Status DMA
2
Register
Result and Flag
of operation Registers
is stored are
in Accumulator. Address Buffer Data/Address Buffer
(8) (8)
part RD
CLK of ALU
ALE S0 S1 IO/M HLDA RESET OUT
READY A7 - A1
54
Bus Bus
INTA RST 6.5 TRAP
A multiplexer pulls
INTRoutRST
the5.5right
RSTgroup
7.5 of bits,SID SOD
depending on the instruction.

8-Bit Internal Data
Two additional 8-bit register,
Bus
which holds the temporary Instructio
data during
Each execution
register can holdof 8-bit n Reg. (8)
W (8) Z (8)
some
data.instructions. Flag (5) Temp. Reg. Temp. Reg.
It increments
They are used
These internally,
registersFlip-Flops
the program can workso in Instruction
counter as B (8) C (8)
Decoder
they
instructions areto
pair not available
hold
execute, 16-bit to the
data
increments and
and and Reg. Reg.
D (8) E (8)
programmer.
decrementstheir the
pairing
stackcombination
pointer as is Machine
Arithmetic
Reg. Reg.
Reg. Select
Logic Unit Register
needed,like andB-C, D-E &(ALU)
supports H-L.
the(8)
16-bit Cycle H (8) L (8)
Array
Encoding Reg. Reg.
increment and decrement instructions.
Stack Pointer (16)

It is a
Supply 16-bit register works
GND Increment/Decrement
likeregister
16-bit stack, which
used tois always
store the memory Address Latch (16)
1
incremented/decremented
address
XThe locationstored
content
CLK of the in
Timing next
the
and instruction
SP and PC
Control to
is
Reset
Control DMA
2by 2 during push & pop
Status
beXexecuted.
loadedGEN
into the address buffer and Address Buffer Data/Address Buffer
operations. buffer.
address-data (8) (8)
The OUTmemory WR and I/O chips are connected
HOLD RESET IN A15 - A8 A7 - A1
to these
READYbuses that can exchange the
55
data. Bus Bus
INTA RST 6.5 TRAP

8-Bit Internal Data
Bus
This unit synchronizes all the microprocessor
Accumulator (8) Temp. Reg. (8) operations
Instructio with the clock and generates control
Multiplexer
n Reg. (8)
signal necessary for Wcommunication
(8) Z (8) between
Flag (5)
microprocessor & peripheral.
Temp. Reg. Temp. Reg.
Decoder Reg. Reg.
and D (8) E (8)
Arithmetic Machine Control
Reg. Signals:
Reg.
Reg. Select
Logic Unit
(ALU) (8)
Cycle READY,
H (8) RD, LWR,
(8) ALE Register
Status Signals:
Stack Pointer (16)
+5 V
S0, S1, Counter
Program
IO/M (16)
Power
Supply
GND DMA Signals:
Increment/Decrement
Address Latch (16)
HOLD, HLDA
X2 GEN Control Status DMA RESET Signals:
RESET
(8)
IN, (8)
CLK RD ALE S0 S1 IO/M HLDA RESET OUT RESET OUT
OUT WR HOLD A15 - A8
READY A7 - A1
RESET IN Address Address/Data
56
Bus Bus
INTA RST 6.5 TRAP
Instructio
Accumulator
It(8)controls
Temp. Reg.
the(8)
interruptsduring a (8)
process. Multiplexer
Itn Reg.
controls the serial data communication by
There are 5 Flag interrupt
(5) signalstwoininstructions:
using 8085 W (8) Z (8)
Temp. Reg. Temp. Reg.
microprocessor:Flip-Flops
i. Instruction
SID (Serial inputB data)
(8) C (8)
INTR, RST 7.5, RST 6.5, RST 5.5,
ii. TRAP.
Decoder Reg.
SOD (Serial output data) Reg.
and D (8) E (8)
Reg. Select
(ALU) (8) H (8) L (8)
Stack Pointer (16)

GND
Address Latch (16)
(8) (8)
READY A7 - A1
57
Bus Bus
INTA RST 6.5 TRAP

8-Bit Internal Data
Bus
Instructio
n Reg. (8)
W (8) Z (8)
Decoder Reg. Reg.
and D (8) E (8)
Reg. Select
(ALU) (8) H (8) L (8)
Stack Pointer (16)

GND
Address Latch (16)
(8) (8)
READY A7 - A1
58
Bus Bus
8085 Microprocessor
Instruction Cycle
Machine Cycle
T-States
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Institute of
of Engineering
Engineering &
& Technology
Technology
Instruction Cycle
Instruction Cycle is defined as time required to complete
execution of an instruction.
8085 instruction cycle consists of 1 to 6 Machine Cycles or 1 to 6
operations.
Instruction Cycle
Fetch Cycle Execute Cycle
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Machine Cycle
Machine Cycle is defined as time required by the microprocessor
to complete operation of accessing memory device or I/O device.
This cycle may consist 3 to 6 T-states.
The basic microprocessor operation such as reading a byte from

I/O port or writing a byte to memory is called as machine cycle.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
T-States
T-States are defined as one subdivision of operation performed in
one clock period.
These sub divisions are internal states synchronized with system
clock & each T-state is precisely equal to one clock period.
T-State1 T-State2 T-State3
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Comparision
Opcode Fetch Memory
Read
Machine Machine
Cycle-1 Cycle-2
Instruction Cycle
Fetch Cycle Execute Cycle
T-State1 T-State2 T-State3 T-State4
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Opcode Fetch
T1 T2 T3 T4
CLK
A8 - A15 High-Order
(PC)H
Address
Low-Order
AD0 - AD7 (PC)L OPCODE Address
ALE
IO/M
S0, S 1 IO/M=0, S0=1, S1=1
Read from
RD Memory
Demultiplexing AD0-AD7
A15 0 A15
0 A14
1 A13
0 High-Order
A12
0 A11 Address Bus
0 A10
0 A9
A8 0 A8
8085 G
ALE Enable
Microprocessor ALE=1
AD7 AD7 0 A7 Address Bus
AD6 0 A6
AD5 0 A5
AD4 0 A4 Low-Order
AD3 1 A3
0 Address Bus
AD2 A2
AD1 1 A1
AD0 AD0 1 A0
0 D ALE= 0
1 D7 Data Bus
0 D6
0 D5 Data Bus
1 D4
1 D3
1 D2
1 D1 65
0
Memory Interfacing
66
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing
When we are executing any instruction, we need the
microprocessor to access the memory for reading instruction
codes and the data stored in the memory.
For this, both the memory and the microprocessor requires some
signals to read/write to/from registers.
The interfacing circuit therefore should be designed in such a way
that it matches the memory signal requirements with the signals
of the microprocessor.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Read Cycle
T1 T2 T3 T4
CLK
A8 - A15 High-Order
(PC)H
Address
Low-Order
AD0 - AD7 (PC)L OPCODE Address
ALE
IO/M
IO/M=0, S0=0, S1=1
S1 S0 Mode S0, S1
0 0 HLT Read from
0 1 WRITE RD Memory
1 0 READ
1 1 OPCODE
FETCH 68
Memory Write Cycle
T1 T2 T3 T4
CLK
A8 - A15 High-Order
(PC)H
Address
Data Low-Order
AD0 - AD7 (PC)L Address
D0-D7
ALE
IO/M
IO/M=0, S0=1, S1=0
S1 S0 Mode S0, S1
0 0 HLT Write
0 1 WRITE WR Memory
1 0 READ
1 1 OPCODE
FETCH 69

Unit-3 8085 Microprocessor: Prof. Swati Sharma

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Unit-3

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

General Purpose Registers

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Size is 16-bits because memory addresses are 16-bits.

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Its function is to point to memory address from which next byte is

Points to the memory location in R/W memory, called Stack.

Beginning of stack is defined by loading a 16-bit address in the

8085 MPU Output Real

8085 MPU Output Real

Group of 8 lines identified as D0 to D7.

They are bidirectional i.e. data flow in both directions between

Largest number appear on data bus is 1111 1111 => (255)10.

As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.

8085 MPU Output Real

Capable of addressing 64K of memory

Requires +5V single power supply

ii. Data Bus

iii. Control & Status Signals

iv. Power Supply & Frequency signals

v. Externally initiated signals

vi. Serial I/O Ports

Pin No.37: This signal can be used

Interrupt Control Serial I/O Control

Stack Pointer (16)

Power +5 V Program Counter (16)

Interrupt Control Serial I/O Control

Stack Pointer (16)

Power +5 V Program Counter (16)

Stack Pointer (16)

Power +5 V Program Counter (16)

depending on the instruction.

Power +5 V Program Counter (16)

Interrupt Control Serial I/O Control

Interrupt Control Serial I/O Control

Stack Pointer (16)

Power +5 V Program Counter (16)

Interrupt Control Serial I/O Control

Stack Pointer (16)

Power +5 V Program Counter (16)

The basic microprocessor operation such as reading a byte from

T-State1 T-State2 T-State3

T-State1 T-State2 T-State3 T-State4

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