Chapter 3

Device Fabrication Technology

About 1020 transistors (or 10 billion for every person in the
world) are manufactured every year.

VLSI (Very Large Scale Integration)

ULSI (Ultra Large Scale Integration)
GSI (Giga-Scale Integration)

Variations of this versatile technology are used for flat-panel

displays, micro-electro-mechanical systems (MEMS), and
chips for DNA screening...

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-1
 3.1 Introduction to Device Fabrication

Oxidation

Lithography &
Etching

Ion Implantation

Annealing &
Diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 3-2
 3.2 Oxidation of Silicon

Quartz tube

Si Wafers

Flow
controller

H 2O or TCE(trichloroethylene) Resistance-heated furnace

O2 N2

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-3
 3.2 Oxidation of Silicon
Dry Oxidation : Si + O2  SiO2

Wet Oxidation : Si +2H2O  SiO2 + 2H2

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-4
 3.2 Oxidation of Silicon
EXAMPLE : Two-step Oxidation
(a) How long does it take to grow 0.1m of dry oxide at 1000 oC ?

(b) After step (a), how long will it take to grow an additional
0.2m of oxide at 900 oC in a wet ambient ?

Solution:

(a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to
grow 0.1m of oxide.

(b) Use the “900oC wet” curve only. It would have taken 0.7hr to
grow the 0.1 m oxide and 2.4hr to grow 0.3 m oxide from
bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-5
 3.3 Lithography
(a) Resist Coating (c) Development
Positive resist Negative resist
Photoresist

Si Oxide

(b) Exposure Si Si

Deep Ultraviolet Light (d) Etching and Resist Strip

Optical Photomask with
Lens system opaque and
clear patterns
Si Si

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-6
 3.3 Lithography
Photolithography Resolution Limit, R
• R kl due to optical diffraction
• Wavelength l needs to be minimized. (248 nm, 193 nm,
157 nm?)
• k (<1) can be reduced will

• Large aperture, high quality lens

• Small exposure field, step-and-repeat using “stepper”
• Optical proximity correction
• Phase-shift mask, etc.
• Lithography is difficult and expensive. There can be 40
lithography steps in an IC process.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-7
 3.3 Lithography

Wafers are being loaded into a stepper in a clean room.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-8
 3.3.1 Wet Lithography

Photo Mask

Water
Photoresist
Wafer

(a) (b)
conventional dry lithography wet or immersion lithography
l l

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-9
 Extreme UV Lithography (13nm wavelength)
Reflective “photomask”
Laser produced
plasma emitting
EUV

No suitable lens material at this

wavelength. Optics is based on mirrors
with nm flatness.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-10
 Beyond Optical Lithography
• Electron Beam Writing : Electron beam(s) scans and exposed
electron resist on wafer. Ready technology with relatively low
throughput.

• Electron Projection Lithography : Exposes a complex

pattern using mask and electron lens similar to
optical lithography.

• Nano-imprint : Patterns are etched into a durable material to

make a “stamp.” This stamp is pressed into a liquid film over
the wafer surface. Liquid is hardened with UV to create an
imprint of the fine patterns.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-11
 3.4 Pattern Transfer–Etching
Isotropic etching Anisotropic etching
photoresist photoresist

SiO 2 SiO 2

(1) (1)

photoresist photoresist

SiO 2 SiO 2

(2) (2)

SiO 2 SiO 2

(3) (3)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
(a) Isotropic wet etching (b) Anisotropic dry etching. Slide 3-12
 3.4 Pattern Transfer–Etching

Reactive-Ion Etching Systems

Gas Baffle
Gas Inlet Wafers

RF RF
Vacuum

Cross-section View Top View

Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-13
 3.4 Pattern Transfer–Etching

Dry Etching (also known as Plasma Etching, or

Reactive-Ion Etching) is anisotropic.

• Silicon and its compounds can be etched by plasmas

containing F.
• Aluminum can be etched by Cl.
• Some concerns :
- Selectivity and End-Point Detection
- Plasma Process-Induced Damage or Wafer Charging
Damage and Antenna Effect

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-14
Scanning electron microscope view of a plasma-etched
0.16 m pattern in polycrystalline silicon film.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-15
 3.5 Doping
3.5.1 Ion Implantation
Dopant ions

• The dominant doping method

• Excellent control of dose (cm-2)
• Good control of implant depth with energy (KeV to MeV)
• Repairing crystal damage and dopant activation requires
annealing, which can cause dopant diffusion and loss of
depth control.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-16
 3.5.1 Ion Implantation
Schematic of an Ion Implanter

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-17
 3.5.1 Ion implantation

Phosphorous density
profile after
implantation

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-18
 3.5.1 Ion Implantation
Model of Implantation Doping Profile (Gaussian)
Ni  ( x  R ) 2 / 2 R 2
N ( x)  e
2  (R)

Ni : dose (cm-2)
R : range or depth
R : spread or sigma

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-19
 Other Doping Methods

• Gas-Source Doping : For example, dope Si with P

using POCl3.

• Solid-Source Doping : Dopant diffuses from a doped

solid film (SiGe or oxide) into Si.

• In-Situ Doping : Dopant is introduced while a Si

film is being deposited.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-20
 3.6 Dopant Diffusion
Junction depth

SiO 2

n-type
diffusion layer
p-type Si

No  x 2 / 4 Dt
N ( x, t )  e
  Dt
N : Nd or Na (cm-3)
No : dopant atoms per cm2
t : diffusion time
D : diffusivity, Dt is the approximate distance of
dopant diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-21
 3.6 Dopant Diffusion
• D increases with
increasing temperature.

• Some applications need

very deep junctions (high
T, long t). Others need
very shallow junctions
(low T, short t).

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-22
 3.6 Dopant Diffusion
Shallow Junction and Rapid Thermal Annealing
• After ion implantation, thermal annealing is required. Furnace
annealing takes minutes and causes too much diffusion of dopants
for some applications.

• In rapid thermal annealing (RTA), the wafer is heated to high

temperature in seconds by a bank of heat lamps.

•In flash annealing (100mS) and laser annealing (<1uS), dopant

ddiffusion is practically eliminated.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-23
 3.7 Thin-Film Deposition
Three Kinds of Solid

Crystalline Polycrystalline Amorphous

Example: Thin film of

Thin film of Si or metal.
Silicon wafer SiO2 or Si3N4.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-24
 3.7 Thin-Film Deposition
Examples of thin films in integrated circuits
• Advanced MOSFET gate dielectric

• Poly-Si film for transistor gates

• Metal layers for interconnects

• Dielectric between metal layers

• Encapsulation of IC

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-25
 3.7.1 Sputtering
Schematic Illustration of Sputtering Process

Sputtering target

Ion (Ar +) Atoms sputtered out of the target

YY Y

Target material
YY deposited on wafer
YYYYY YY YYY YYYYYYYY
YYYYYYYY YYYYYY YYYY YYYYYY
YYYYYYYY YYYYYY YYYYYYYYYYYY
YYYYYYYY YYYYYY YYYYYYYYYYYY YY
Y YYYY
YYYYY YYYYYYY YYYYYYY
YYYY
YY YYYYYY YYYYYYY
YY YYYY YYYYYYYY
YYYYYYYYYYYY
YYY YYYYYY
Y YY

Si Wafer

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-26
 3.7.2 Chemical Vapor Deposition (CVD)

Thin film is formed from gas phase components.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-27
 Some Chemical Reactions of CVD

Poly-Si : SiH4 (g) Si (s) + 2H2 (g)

Si3N4 : 3SiH2Cl2 (g)+4NH3 (g) Si3N4 (s)+6HCl(g)+6H2 (g)

SiO2 : SiH4 (g) + O2 (g) SiO2 (s) + 2H2 (g)

or
SiH2Cl2 (g)+2N2O (g) SiO2 (s)+2HCl (g)+2N2 (g)

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-28
 3.7.2 Chemical Vapor Deposition (CVD)

Two types of CVD equipment:

• LPCVD (Low Pressure CVD) : Good uniformity.

Used for poly-Si, oxide, nitride.

• PECVD (Plasma Enhanced CVD) : Low temperature

process and high deposition rate. Used for oxide,
nitride, etc.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-29
 3.7.2 Chemical Vapor Deposition (CVD)
Pressure sensor Resistance-heated furnace
Quartz tube
Trap
To exhaust
Si Wafers

Pump
Source
gases
Gas control
system
LPCVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-30
 3.7.2 Chemical Vapor Deposition (CVD)

Cold Wall Parallel Plate

Gas Injection Wafers

Ring
Pump
Heater Coil
Wafers

Gas Pump
Hot Wall Parallel Plate Inlet Power leads

Plasma Electrodes

PECVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-31
3.7.3 Epitaxy (Deposition of Single-Crystalline Film)
Epitaxy Selective Epitaxy
SiO 2 SiO2

Si Substrate Si Substrate

Epi film SiO 2 Epi film SiO2

Si Substrate Si Substrate

(a) (b)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-32
3.8 Interconnect – The Back-end Process
AlAl-Cu
or Cu

SiO2

Dopant diffusion region

Si

(a)
Encapsulation

Metal 3

Dielectric
Metal 2
via or plug
Dielectric
Metal 1

Dielectric

silicide
CoSi2
diffusion region
Si

(b)

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-33
 3.8 Interconnect – The Back-end Process
SEM: Multi-Level Interconnect (after removing the dielectric)

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-34
 3.8 Interconnect – The Back-end Process

Copper Interconnect
• Al interconnect is prone to voids formation by
electromigration.
• Cu has excellent electromigration reliability
and 40% lower resistance than Al.
• Because dry etching of copper is difficult (copper
etching products tend to be non-volatile), copper
patterns are defined by a damascene process.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-35
 3.8 Interconnect – The Back-end Process
Copper Damascene Process

dielectric dielectric

(a) (b) •Chemical-Mechanical

Polishing (CMP)
removes unwanted
Cu
materials.
Cu
•Barrier liner prevents
liner liner Cu diffusion.
dielectric dielectric

(c) (d)

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-36
 3.8 Interconnect – The Back-end Process

Planarization

• A flat surface is highly desirable for subsequent

lithography and etching.

• CMP (Chemical-Mechanical Polishing) is used

to planarize each layer of dielectric in the
interconnect system. Also used in the front-end
process.

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-37
 3.9 Testing, Assembly, and Qualification

• Wafer acceptance test

• Die sorting
• Wafer sawing or laser cutting
• Packaging
• Flip-chip solder bump technology
• Multi-chip modules
• Burn-in
• Final test
• Qualification

Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Slide 3-38
 P-Si

SiO2 SiO2 (11)

(3)
3.10 Chapter Summary–A Device Fabrication
P-Si Example
Arsenic implantation SiO
(4) Ion
(0) P-Si (8)SiO Al
Wafer 2
S iO2 SiO2 S iO
2
Implantation
P-Si N+
SiO2 P (12)
(1)
P-Si SiO 2 SiO2
Oxidation (5) (9) N+
SiO2 Si3 N4 Annealing & SiO
P Al
SiO2 SiO Diffusion
UV N+
2

UV (6) Al
SiO2 P2
SiO
(2) N+
M ask Al
(10) PSi
3 N4 Sputtering
Positive resist Al (13) Si
SiO2 UV
SiO2 UV SiO2
Lithography N+ SiO2
P-Si M as k P
SiO2 SiO2 (7) (11)Res is t Photoresist
(3) Al Al
P-Si SiO2 SiO2
Etching NSi
+ 3 N4

Arsenic implantation P Al
SiO2 SiO 2
N+
(4) Lithography
SiO2 SiO2 P

P-Si
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-39
(12) Si3 N4
SiO 2 SiO2 Al
 (3) SiO2 SiO2 Photoresist
P-Si
Si3 N4
Arsenic implantation Al
3.10 Chapter Summary–A Device Fabrication Example SiO2
N+
SiO 2
(4)
SiO2 SiO2 P

P-Si Al
Metal (8) S iO2 S iO2
N+ (12) Si3 N4 Back side
etching SiO SiO2
(5)
2
P Al
N+ SiO2 SiO 2 metallization
P N+

CVD (9) Si3 N4 P

Al
nitride
(6) Al SiO2 SiO2
deposition SiO2 N SiO2
+ Au
N+ P
P wire
(10) Si3 N4 (13) Si3N 4
Lithography UV Al Al
and etching SiO2 SiO2 SiO2 SiO2
M as kN
+
+
N
P P
(7) Res is t
(11) Al
2 Photoresist Al
Au
SiO2 SiO2
SiN3 N4
+
Plastic package
Back Side P Al
milling SiO2 SiO 2 metal leads
N+

2
P Dicing, wire bonding,
and packaging
(12) Si3 N4
Modern Semiconductor
Al Devices for Integrated Circuits (C. Hu) Slide 3-40
SiO2 SiO 2
N+