Coa Co2

15EM2001
COMPUTER ORGANIZATION AND ARCHITECTURE
© 2016 KL University – The contents of this presentation are an intellectual and

1
copyrighted property of KL University. ALL RIGHTS RESERVED
CPU Design

2
Introduction to CPU
The operation or task that must perform by CPU are:
•Fetch Instruction
•Interprete Instruction
•Fetch Data
•Process data
•Write data

3
•The major components of the CPU are an arithmetic and
logic unit (ALU) and a control unit (CU).
•The ALU does the actual computation or processing of
data.
•The CU controls the movement of data and instruction
into and out of the CPU and controls the operation of the
ALU.
4
CPU system Bus
5
CPU System Bus
The system bus may have three components:

1. Data Bus
2. Address Bus
3. Control Bus

6
Internal Structure of the CPU

7
There are three basic components of CPU:
1. Register bank
2. ALU and
3. Control Unit.
•There are several data movements between these units

and for that an internal CPU bus is used.

8
Register Organization
The registers in the CPU can be categorized into two groups:
•User-visible registers
•Control and status registers
User-visible Registers:
•General Purpose Registers
•Data Registers
•Address Registers
•Condition Codes
9
Address registers:
•Segment pointer
•Index registers
•Stack pointer
Four registers are essential to instruction execution:
1. Program Counter (PC)
2. Instruction Register (IR)
3. Memory Address Register (MAR)
4. Memory Buffer Register (MBR)
10
Processor Status
Word
1. Sign
2. Zero
3. Carry
4. Equal
5. Overflow
6. Interrupt enable/disable
7. Supervisor
11
Concept of Program Execution
1. Fetch the contents of the memory location pointed at by the PC. The
contents of this location are interpreted as an instruction to be executed.
Hence, they are stored in the instruction register (IR). Symbolically this can be
written as:
IR = [ [PC] ]
2. Increment the contents of the PC by 1.
PC = [PC] + 1
3. Carry out the actions specified by the instruction stored in the IR.
12
Single bus organization of the data path
inside the CPU

13
The processor interpretes the instruction and performs the
required action. In general, the actions fall into four categories:
•Processor-memory
•Processor-I/O
•Data processing
•Control
14
Instruction cycle
Basic Instruction cycle

15
An instruction cycle consists of two phase,
1. Fetch cycle
2. Execution cycle
Operation of a CPU:
1. Fetch the contents of a given memory location and load them into a CPU
register.
2. Store a word of data from a CPU register into a given memory location.
3. Transfer a word of data from one CPU register to another or to the ALU.
4. Perform an arithmetic or logic operation, and store the result in a CPU register
16
8086 ARCHITECTURE

17
Addressing Modes
The most common addressing techniques are:
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement
• Stack
18
To explain the addressing modes, the following notationis used:
A = contents of an address field in the instruction that refers to a

memory
R = contents of an address field in the instruction that refers to a

register
EA = actual (effective) address of the location containing the referenced

operand
(X) = contents of location X

19
Immediate Addressing
The simplest form of addressing is immediate addressing
OPERAND = A
Instruction
Opcode Operand

20
Direct Addressing
•
Address field contains address of operand

•
Effective address (EA) = address field (A)

•
e.g. ADD A
•
Add contents of cell A to accumulator

•
Look in memory at address A for operand

•
Single memory reference to access data

•
No additional calculations to work out effective address

•
Limited address space

21
Direct Addressing Diagram
Instruction
Address A
Memory
Operand

22
Indirect Addressing
Memory cell pointed to by address field contains the address

of (pointer to) the operand
•
EA = (A)
Look in A, find address (A) and look there for operand
•
e.g. ADD (A)

Add contents of cell pointed to by contents of A to accumulator
•

23
Indirect Addressing Diagram
Instruction
Address A
Memory
Pointer to operand
Operand

24
Register Addressing
•
Operand is held in register named in address filed

•
EA = R
•
Limited number of registers

•
Very small address field needed

Shorter instructions
•
Faster instruction fetch

•

25
Register Addressing
•
No memory access
•
Very fast execution

•
Very limited address space

•
Multiple registers helps performance

Requires good assembly programming or compiler writing
•
Direct addressing

26
Register Addressing Diagram
Instruction
Register Address R
Registers
Operand

27
Register Indirect Addressing
•
Indirect addressing
•
EA = (R)
•
Operand is in memory cell pointed to by contents of register

R
•
Large address space (2n)

•
One fewer memory access than indirect addressing

28
Register Indirect Addressing
Instruction
Opcode Register Address R

Memory
Registers
Pointer to Operand Operand

29
Displacement Addressing
•
EA = A + (R)
•
Address field hold two values

A = base value
•
R = register that holds displacement

•
or vice versa
•

30
Displacement Addressing Diagram

31
•
Relative Addressing
•
Base-Register Addressing
•
Indexing
auto-indexing
•
auto-incrementing
•
EA = A + (R)
•
R = (R) + 1
•

32
auto-decrementing
•
EA = A + (R)
•
R = (R) – 1
•
If indexing is performed after the indirection, it is termed

postindexing
EA = (A) + (R)
•
With preindexing, the indexing is performed before the

indirection:
EA = ( A + (R) )

33
Stack Addressing
•
Operand is (implicitly) on top of stack

•
e.g.
ADD Pop top two items from stack and add
•

34
Instruction Set
•
The operation of a CPU is determine by the instruction it

executes, referred to as machine instructions or computer
instructions. The collection of different instructions is referred
as the instruction set of the CPU.
•
Each instruction must contain the information required by the

CPU for execution.

35
Opcodes are represented by abbreviations, called
mnemonics, that indicate the operations
4-bits 6-bits 6-bits
Opcode Operand1 Operand2
A simple instruction format

36
The instruction set of a CPU can be categorized as follows:
1. Data Processing
2. Data Storage
3. Data Movement
4. Control
Types of Operands
1. Addresses
2. Numbers
3. Characters
4. Logical Data
37
Types of Operations
•
Data Transfer
•
Arithmetic
•
Logical
•
Conversion
•
Input Output [ I/O ]

•
System Control
•
Transfer Control

38
A. Data Transfer
Move (Transfer) --------Transfer word or block from source to destination
Store ----------------------Transfer word from processor to memory
Load (fetch) -------------Transfer word from memory to processor
Exchange ----------------Swap contents of source and destination
Clear (reset)------------- Transfer word of 0s to destination
Set -------------------------Transfer word of 1s to destination
Push -----------------------Transfer word from source to top of stack
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B. Arithmetic
Add --------------Compute sum of two operands
Subtract --------Compute difference of two operands
Multiply ---------Compute product of two operands
Divide -----------Compute quotient of two operands
Absolute --------Replace operand by its absolute value
Negate ----------Change sign of operand
Increment ------Add 1 to operand
Decrement -----Subtract 1 from operand

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C. Logical
AND -----------------------Performs the logical operation AND bitwise
OR--------------------------Performs the logical operation OR bitwise
NOT -----------------------Performs the logical operation NOT bitwise
Exclusive OR -------------Performs the specified logical operation Exclusive-OR
bitwise
Test --------------------------Test specified condition; set flag(s) based on outcome
Compare -------------------Make logical or arithmetic comparison Set flag(s)
based on outcome
Set Control Variables------Class of instructions to set controls for protection
purposes, interrupt handling, timer control etc.
Shift -----------------------Left (right) shift operand, introducing constant at end
Rotate --------------------Left (right) shift operation, with wraparound end

41
D. Input/output
Input (Read)----- Transfer data from specified I/O port or device to
destination (e.g., main memory or processor register)
Output (Write)----Transfer data from specified source to I/O port or

device.
Start I/O------------ Transfer instructions to I/O processor to initiate

I/O operation.
Test I/O --------------Transfer status information from I/O system to

specified destination
42
E. System Control
System control instructions are those which are

used for system setting and it can be used only in
privileged state.
Typically, these instructions are reserved for the

use of operating systems.

43
F. Transfer of Control
•
The most common transfer-of-control operations

found in instruction set are:
Branch
Skip
Procedure call.
44
BRP X ----Branch to location X if result is positive
BRN X ---- Branch to location X if result is negative
BRZ X----- Branch to location X is result is zero
BRO X----- Branch to location X if overflow occurs

45
Instruction Format
Opcode Zero Address Instruction
Opcode Address One Address Instruction
Opcode Address1 Address2 Two Address Instruction
Opcode Address1 Address2 Address3

Three Address Instruction
Example: X = (A + B) * (C + D)
46
Three address instructions
ADD R1 , A , B R 1 <--M [ A ] + M [ B ]
ADD R2 , C , D R 2 <--M [ C ] + M [ D ]
MUL X , R1 , R2 M [ X ] <--R 1 * R 2
Two address instructions
MOV R1 , A R 1 <--M [ A ]
ADD R1 , B R 1 <--R 1 + M [ B ]
MOV R2 , C R 2 <--M [ C ]
ADD R2 , D R 2 <--R 2 + M [ D ]
MUL R1 , R2 R 1 <--R 1 * R 2
MOV X , R1 M [ X ] <--R 1
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One address instructions
LOAD A A C <- M [ A J
ADD B A C <- A C + M [ B ]
STORE T M [ T ] <- A C
LOAD C A C <- M [ C ]
ADD D A C <- A C + M [ D ]
MUL T A C <- A C • M [ T ]
STORE X M [ X ] <- A C

48
Zero address instructions

49
Stack Organization
Block diagram of 64- word stack

50
Subroutine Calls
Requirements
Set PC to arbitrary address
Return PC to instruction after call sequence
Handle nested subroutine calls
Save and restore caller’s registers
Pass an arbitrary number of arguments
Pass and return structures
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Common Micro-Ops
There are 4 types of Micro-Ops:
Transfer: transfers data from one register to another

R0 <- R1
•
Arithmetic: performs arithmetic on data in registers

R0 <- R1 + R2
•
Logic/bit manipulation: performs bit (Boolean) operations on data

R0 <- R1 & R2 ; or R0 <- R1 | R2
•
Shif: shift data in registers by one or more bit positions

R0 <- R1 << 3; or R0 <- R2 >> 2

53
Micro-Ops Transfer
Parallel
Parallel transfer is typically used

for transfers between registers

Ex: Transfer all contents of A

into B on one clock pulse

A <- B
Control function: we can do this

by structuring the RTL expression to

indicate the controlling condition
Ex: P: A<- B


54
Micro-Ops Transfer
Serial 
Serial transfer is used to specify

that a collection of bits are to be
moved, but that the transfer is to
occur one bit at a time
Ex: S: A <- B, B <-B

55
Micro-Ops Transfer
Bus
A bus consists of a set of parallel data lines

To transfer data using a bus: connect the output of the source register to the bus; connect

the input of the target register to the bus; when the clock pulse arrives, the transfer occurs

56
Micro-Ops Transfer
Memory
Memory transfers are similar to register transfers, but…

Memory to register transfers are called read operations, while


register to memory transfers are called write operations

RTL expressions for a read operation, assuming the use of an address registers:

AR <- address
DR <- M[AR]
RTL expressions for a write operation, assuming use of a data register:

AR <- address
DR <- value
M[AR] <- DR

57
MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000 LDA Routine
. 0010
AND 0001 STA Routine
. 0011
LDA 0010 . 0100 BUN Routine
STA 0011 Control
BUN 0100 Storage
Mapping
10 xxxx 010
Bits Address
10 0000 010 ADD Routine
10 0001 010 AND Routine

10 0010 010 LDA Routine
10 0011 010 STA Routine

10 0100 010 BUN Routine
© 2016 KL University – The contents of this presentation are an intellectual and 58

MACHINE INSTRUCTION FORMAT
Machine instruction format
15 14 11 10 0
I Opcode Address
Micro-instruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
59
Sample machine instructions
Symbol Opcode Description
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC M[EA], M[EA]  AC
EA is the effective address

60
MICROINSTRUCTION FIELD DESCRIPTIONS
- F1,F2,F3
F1 Micro Symbol F2 Micro Symbol F3 Micro Symbol
operation operation operation
000 None NOP 000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB 001 AC  AC XOR

DR
010 AC  0 CLRAC 010 AC  AC  DR OR 010 AC  AC' COM

011 AC  AC + 1 INCAC 011 AC  AC  DR AND 011 AC  shL AC SHL
100 AC  DR DRTAC 100 DR  M[AR] READ 100 AC  shr AC SHR
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR 101 PC  PC + 1 INCPC
110 AR  PC PCTAR 110 DR  DR + 1 INCDR 110 PC  AR ARTPC
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR 111 RESERVED

61
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD Condition Symbol Comments
00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
62
DESIGN OF CONTROL UNIT
DECODING ALU CONTROL INFORMATION -
microoperation fields
F1 F2 F3
3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 7 6 54 3 21 0
AND
ADD Arithmetic AC
DRTAC logic and
shift unit DR
PCTAR
DRTAR
From From
PC DR(0-10) Load
AC
Select 0 1
Multiplexers
Load AR Clock
Decoding of Microoperation Fields

63
Memory
1. Concept of Memory.
2. Cache Memory.
3. Memory Management
4. Virtual memory
The memory of computer is broadly categories into
two categories:
•Internal Memory or Primary Memory
• External Memory or Secondary Memory

64
Primary Memory
•
RAM: Random Access Memories are volatile in nature. As

soon as the computer is switched off, the contents of
memory are also lost.
•
Types: SRAM, DRAM
ROM: Read only memories are non volatile in nature. The

storage is permanent, but it is read only memory. We can not
store new information in ROM.
•
Types: PROM, EPROM, EEPROM, UVPROM

65
Main Memory Organization
•
16X4 Means 16 Locations & 4 bits in each Location
Read – Retrieve data from memory to CPU registers

•
Write – Store data to memory from CPU registers
To transfer data we require data bus
To specify or to identify a particular memory location we require

address bus

66
Semiconductor Memory Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random EPROM Mask-Programmed

Access Access
2
E PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
Content
Addressable
Memory (CAM)

67
RAM
•
Random write and read operation for any cell

•
Volatile data
•
Most of computer memory

•
DRAM
•
Low Cost
•
High Density
•
Medium Speed
•
SRAM
•
High Speed
•
Ease of use
•
Medium Cost
68
ROM
•
Non-volatile Data
•
Method of Data Writing

•
Mask ROM
Data written during chip fabrication
•
PROM
Fuse ROM: Non-rewritable
•
EPROM:
•
Erase data by UV rays

EEPROM: Erase and write through electrical means
•
Speed 2-3 times slower than RAM

•
Upper limit on write operations

•
Flash Memory – High density, Low Cost

69
FLASH
•
Extension of EEPROM
•
Same floating gate principle

•
Same write ability and storage permanence

•
Fast erase
•
Large blocks of memory erased at once, rather than one word at a time
•
Blocks typically several thousand bytes large

•
Writes to single words may be slower

•
Entire block must be read, word updated, then entire block written back
•
Used with embedded microcomputer systems storing large data items in nonvolatile
memory
•
e.g., digital cameras, MP3, cell phones

70
CPU and Memory
•
CPU can interact with main memory in two ways:

•It can write a byte/word to a given memory location.
•The previous bits that were in that location are destroyed
•The new bits are saved for future use.
•It can read a byte/word from a given memory location.
•The CPU copies the bits stored at that location and stores them in a CPU register
•The contents of the memory location are NOT changed.

71
Main Memory Characteristics

Very closely connected to the CPU.


Contents are quickly and easily changed.


Holds the programs and data that the processor is actively working
with.

Interacts with the processor millions of times per second.


Nothing permanent is kept in main memory.

72
Secondary Storage Characteristics
Connected to main memory through a bus and a device controller.


Contents are easily changed, but access is very slow compared to

main memory.

Only occasionally interacts with CPU.


Used for long-term storage of programs and data.


Much larger than main memory (GBs vs. MBs).

73
•
CPU --- Memory Hi Lo

•
16-bit CPU Byte Organized
Data Size Lower order byte

first or little endian
15-8 7-0 Hi CPU
Lo
Higher order byte

first or Big endian
Lo CPU
Hi

74
The data transfer between main memory and the CPU takes place
through two CPU registers.
MAR : Memory Address Register
MDR : Memory Data Register.
If the MAR is k-bit long, then the total addressable memory

location will be 2k.
If the MDR is n-bit long, then the n bit of data is transferred in one
memory cycle.

75
Binary Storage Cell

76
Depending on the technology used to construct a RAM,
there are two types of RAM –
SRAM: Static Random Access Memory.
DRAM: Dynamic Random Access Memory
SRAM
77
DRAM
SRAM & DRAM both are volatile
DRAM packing density is more & Less expensive
DRAM requires supporting refresh circuitry
SRAM is faster than DRAM

78
79
80
Memory Management
Five State Process Model

81
Memory Management
1. Uni- Program
2. Multi –Program Memory
Operating System
Uni-Program:
Memory split into two User Program

1. For operating system
2. For currently executing program
Uni-Program
82
Memory Management
Memory
Multi-Program:
Operating System
Memory split into multiple

User Program 1
1. For operating system
User Program 2
2. User part of memory is subdivided to ac
commodate multiple processes. User Program 3
Multi-Program

83
Partitioni
ng
1) Fixed size partitions
2) Variable size partitions

84
Paging
The memory is partitioned into equal fixed size chunks that are relatively
small. This chunk of memory is known as frames or page frames.
Each process is also divided into small fixed chunks of same size. The
chunks of a program is known as pages.
At a given point of time some of the frames in memory are in use and some
are free. The list of free frame is maintained by the operating system.

85
86
87
Cache Memory
It is the fact that CPU is a faster device and memory is a relatively
slower device.
Memory access is the main bottleneck for the performance efficiency. If

a faster memory device can be inserted between main memory and
CPU, the efficiency can be increased.
The faster memory that is inserted between CPU and Main Memory is
termed as Cache memory.

88
Cache Memory
•
High speed (towards CPU speed)

•
Small size (power & cost)

Miss
Main
CPU Memory
Cache (Slow)
(Fast)  Mem
Hit Cache
95% hit ratio

 Access = 0.95
© 2016 KL University – The contents  Cache + 0.05
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are anMem
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89
Cache Memory
CPU 30-bit Address

Main
Memory
Cache
1 Gword
1 Mword
Only 20 bits !!!

90
Cache Mapping
1. Direct mapping
2. Associative mapping
3. Block-set-associative mapping

91
Direct Mapping
•
A particular block of main

memory can be brought to a
particular block of cache
memory.
•
It is not flexible

92
Associative Mapping
•
In this mapping function, any

block of Main memory can
potentially reside in any cache
block position.
•
This is much more flexible

mapping method.

93
Block Set Associative Mapping
•
In this method, blocks

of cache are grouped
into sets, and the
mapping allows a block
of main memory to
reside in any block of a
specific set. From the
flexibility point of view,
it is in between to the
other two methods

94
Cache Replacement Policies
1. Least Recently Used (LRU) replacement policy
2. First In First Out (FIFO) replacement policy
3. Random replacement policy

95
Virtual Memory
The virtual address space is used to develop a process. The special hardware unit , called
Memory Management Unit (MMU) translates virtual address to physical address. When
the desired data is in the main memory, the CPU can work with these data. If the data are
not in the main memory, the MMU causes the operating system to bring into the memory
from the disk.

96
VIRTUAL MEMORY
Relation between memory space and address in a virtual memory system

97
Memory table for mapping a virtual address

98
Address space and memory space split into groups of lK words.
99
Memory Table in a paged system
100
An associative memory page table.
101

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15EM2001

COMPUTER ORGANIZATION AND ARCHITECTURE

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

The system bus may have three components:

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

•There are several data movements between these units

© 2016 KL University – The contents of this presentation are an intellectual and

2. Increment the contents of the PC by 1.

© 2016 KL University – The contents of this presentation are an intellectual and

Basic Instruction cycle

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

A = contents of an address field in the instruction that refers to a

R = contents of an address field in the instruction that refers to a

EA = actual (effective) address of the location containing the referenced

(X) = contents of location X

© 2016 KL University – The contents of this presentation are an intellectual and

The simplest form of addressing is immediate addressing

© 2016 KL University – The contents of this presentation are an intellectual and

Address field contains address of operand

Effective address (EA) = address field (A)

Add contents of cell A to accumulator

Look in memory at address A for operand

Single memory reference to access data

No additional calculations to work out effective address

Limited address space

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

Memory cell pointed to by address field contains the address

e.g. ADD (A)

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

Operand is held in register named in address filed

Limited number of registers

Very small address field needed

Faster instruction fetch

© 2016 KL University – The contents of this presentation are an intellectual and

Very fast execution

Very limited address space

Multiple registers helps performance

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

Operand is in memory cell pointed to by contents of register

Large address space (2n)

One fewer memory access than indirect addressing

© 2016 KL University – The contents of this presentation are an intellectual and

Opcode Register Address R

Pointer to Operand Operand

© 2016 KL University – The contents of this presentation are an intellectual and

Address field hold two values

R = register that holds displacement

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

© 2016 KL University – The contents of this presentation are an intellectual and

If indexing is performed after the indirection, it is termed

With preindexing, the indexing is performed before the

© 2016 KL University – The contents of this presentation are an intellectual and

Operand is (implicitly) on top of stack

© 2016 KL University – The contents of this presentation are an intellectual and

The operation of a CPU is determine by the instruction it