CEIEC

The FPGA implementation of the

digital receiver
FPGA implementation of the digital receiver CEIEC

Poly phase
 AD input N times Poly phase
decimation filter

PDW output
Parameter
code Detection

FPGA implementation of the poly-phase digital receiver

FPGA implementation of the digital receiver CEIEC

N times decimation
FPGA implementation of the digital receiver CEIEC

Reorder after N times decimation

FPGA implementation of the digital receiver CEIEC

Data from unsigned to signed

FPGA implementation of the digital receiver CEIEC

Data from unsigned to signed

FPGA implementation of the digital receiver CEIEC

N times decimation
The A/D output data could be 2 or 4 times decimated.
8 times decimation can be achieved when the data received by FPGA is
processed by the decimation IP core.
After the decimation, the data stream will be recovered to original one
by order sorting .
 the data should be changed from unsiged to signed for after-processing
FPGA implementation of the digital receiver CEIEC

Poly phase filter


FPGA implementation of the digital receiver CEIEC

Poly phase


FPGA implementation of the digital receiver CEIEC

Poly phase filter


FPGA implementation of the digital receiver CEIEC

Poly phase filter


FPGA implementation of the digital receiver CEIEC

Poly phase filter

 The coefficient of prototype filter is obtained in MATLAB, and then

amplified and take the round figure with certain bit.
 Achieve multi-stage delay for the input signal by introducing
multiple variables.
 Introduce for loop to reduce the VHDL code editing load.
 It multiplies or divides a constant in the operation in order to
increase or decrease the parameter in order to avoid that some figure
is too large or too small. (in order to reduce the consumption of logical
resource, the constant is generally 2n such as 64, 128, etc. )
FPGA implementation of the digital receiver CEIEC

IFFT
FPGA implementation of the digital receiver CEIEC

IFFT
FPGA implementation of the digital receiver CEIEC

IFFT

twiddle factor
FPGA implementation of the digital receiver CEIEC

IFFT
FPGA implementation of the digital receiver CEIEC

IFFT
IFFT is realized by FFT, that is, take the conjugation for the input and
output of FFT.
As the input is parallel, it is not advised to adopt FFTIP core which is
applied for serial input.
Twiddle factor is calculated and saved in the FPFA register in advance.
The data with certain bit could be obtained by the amplification and
rounding.
Radix 2 or radix 4 structure could be applied based on the FFT points,
which can achieved in the MATLAB simulation.
FPGA implementation of the digital receiver CEIEC

Detector
FPGA implementation of the digital receiver CEIEC

Detector

Men_const:weak or no signal threshold

Con_h/men5_h: some channels high threshold
Con_l/men5_l: some channels low threshold
Men_h/men_l: threshold factor
Cun: detector output – signal is present in channel + PW as a
pulse
FPGA implementation of the digital receiver CEIEC

Detector
FPGA implementation of the digital receiver CEIEC

PDW coder

TOA: Time of arrival

TOE: Time of end

PW=TOE-TOA
FPGA implementation of the digital receiver CEIEC

PDW coder

Calculate FFT of channel signal, measure the

FFT amplitude, and then calculate the pick
amplitude value of the FFT to estimate the
signal frequency in the channel

We use 4 parallel FFT IP cores to measure

signal frequency of 4 different channels
Simultaneously – the probability of having
More than 4 or 6 signals at a time is very
small
FPGA implementation of the digital receiver CEIEC

PDW coder
FREQUENCY CODE
Superheterodyne receiver IF processor CEIEC

IF processor performs the digital processing for the IF signal output from the front
end, and output the pulse description word.

IF processing

It includes A/D sampling, DDC down conversion, FFT frequency measurement, signal
detection, and Parameter encoding.
Superheterodyne receiver IF processor CEIEC

DDC digital down conversion

DDC is a process to remove the carrier frequency of the input IF signal, and convert it
to baseband (zero IF).

DDC principle
0
 is the carrier frequency of the input signal, mixing with the digital local
oscillator and down to zero IF.
FPGA implementation of the digital receiver CEIEC

LO GENERATOR
FPGA implementation of the digital receiver CEIEC

LO GENERATOR

NCO IP CORE
FPGA implementation of the digital receiver CEIEC

LO GENERATOR

Parameter
Setting
FPGA implementation of the digital receiver CEIEC

LO GENERATOR

Parameter
Setting
FPGA implementation of the digital receiver CEIEC

LO GENERATOR

Phase
Accumulate
Word setting
FPGA implementation of the digital receiver CEIEC

Digital Mixer

I channel

Q channel
FPGA implementation of the digital receiver CEIEC

Lpm_mult symbol use

FPGA implementation of the digital receiver CEIEC

Lpm_mult symbol use

FPGA implementation of the digital receiver CEIEC

FIR low pass filter

FPGA implementation of the digital receiver CEIEC

FIR low pass filter

FPGA implementation of the digital receiver CEIEC

FIR low pass filter

Filter coefficient

input delay
FPGA implementation of the digital receiver CEIEC

FIR low pass filter

Mult and add

arithmetic
FPGA implementation of the digital receiver CEIEC

Decimation
FPGA implementation of the digital receiver CEIEC

Decimation clk generator

FPGA implementation of the digital receiver CEIEC

Decimation clk generator

FPGA implementation of the digital receiver CEIEC

Decimation clk generator

FPGA implementation of the digital receiver CEIEC

Decimation clk generator

 CEIEC

FPGA design basic steps

 1 create a new project

2 create a new module(or file)

3 compilation

4 simulation and debug

 CEIEC

create a new project


 CEIEC

create a new module

 a project consists of many modules
usually two ways: schematic file and HDL
file(VHDL or Verilog)

Some constant logic unit can be used

by the schematic way
such as DFF/ COUNTER etc.
 CEIEC

create a new module


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create a new module


 CEIEC

create a new module

 IP CORE often used to
improve the design speed and
quality

Most used types:

DSP
I/O
Memory Compiler
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create a new module(HDL file way)


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create a new module(HDL file way)


VHDL

Keyword: process
 CEIEC

create a new module(HDL file way)


 CEIEC

create a new module(HDL file way)

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Simulation
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Simulation
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Simulation
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