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Device Fabrication Technology: Modern Semiconductor Devices For Integrated Circuits (C. Hu) Slide 3-1
Device Fabrication Technology: Modern Semiconductor Devices For Integrated Circuits (C. Hu) Slide 3-1
Oxidation
Lithography &
Etching
Ion Implantation
Annealing &
Diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 3-2
3.2 Oxidation of Silicon
Quartz tube
Si Wafers
Flow
controller
(b) After step (a), how long will it take to grow an additional
0.2m of oxide at 900 oC in a wet ambient ?
Solution:
(a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to
grow 0.1m of oxide.
(b) Use the “900oC wet” curve only. It would have taken 0.7hr to
grow the 0.1 m oxide and 2.4hr to grow 0.3 m oxide from
bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-5
3.3 Lithography
(a) Resist Coating (c) Development
Positive resist Negative resist
Photoresist
Si Oxide
(b) Exposure Si Si
Photo Mask
Water
Photoresist
Wafer
(a) (b)
conventional dry lithography wet or immersion lithography
l l
SiO 2 SiO 2
(1) (1)
photoresist photoresist
SiO 2 SiO 2
(2) (2)
SiO 2 SiO 2
(3) (3)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
(a) Isotropic wet etching (b) Anisotropic dry etching. Slide 3-12
3.4 Pattern Transfer–Etching
Gas Baffle
Gas Inlet Wafers
RF RF
Vacuum
Phosphorous density
profile after
implantation
Ni : dose (cm-2)
R : range or depth
R : spread or sigma
SiO 2
n-type
diffusion layer
p-type Si
No x 2 / 4 Dt
N ( x, t ) e
Dt
N : Nd or Na (cm-3)
No : dopant atoms per cm2
t : diffusion time
D : diffusivity, Dt is the approximate distance of
dopant diffusion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-21
3.6 Dopant Diffusion
• D increases with
increasing temperature.
• Encapsulation of IC
Sputtering target
Target material
YY deposited on wafer
YYYYY YY YYY YYYYYYYY
YYYYYYYY YYYYYY YYYY YYYYYY
YYYYYYYY YYYYYY YYYYYYYYYYYY
YYYYYYYY YYYYYY YYYYYYYYYYYY YY
Y YYYY
YYYYY YYYYYYY YYYYYYY
YYYY
YY YYYYYY YYYYYYY
YY YYYY YYYYYYYY
YYYYYYYYYYYY
YYY YYYYYY
Y YY
Si Wafer
Pump
Source
gases
Gas control
system
LPCVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-30
3.7.2 Chemical Vapor Deposition (CVD)
Gas Pump
Hot Wall Parallel Plate Inlet Power leads
Plasma Electrodes
PECVD Systems
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-31
3.7.3 Epitaxy (Deposition of Single-Crystalline Film)
Epitaxy Selective Epitaxy
SiO 2 SiO2
Si Substrate Si Substrate
Si Substrate Si Substrate
(a) (b)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-32
3.8 Interconnect – The Back-end Process
AlAl-Cu
or Cu
SiO2
(a)
Encapsulation
Metal 3
Dielectric
Metal 2
via or plug
Dielectric
Metal 1
Dielectric
silicide
CoSi2
diffusion region
Si
(b)
Copper Interconnect
• Al interconnect is prone to voids formation by
electromigration.
• Cu has excellent electromigration reliability
and 40% lower resistance than Al.
• Because dry etching of copper is difficult (copper
etching products tend to be non-volatile), copper
patterns are defined by a damascene process.
dielectric dielectric
(c) (d)
Planarization
UV (6) Al
SiO2 P2
SiO
(2) N+
M ask Al
(10) PSi
3 N4 Sputtering
Positive resist Al (13) Si
SiO2 UV
SiO2 UV SiO2
Lithography N+ SiO2
P-Si M as k P
SiO2 SiO2 (7) (11)Res is t Photoresist
(3) Al Al
P-Si SiO2 SiO2
Etching NSi
+ 3 N4
Arsenic implantation P Al
SiO2 SiO 2
N+
(4) Lithography
SiO2 SiO2 P
P-Si
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 3-39
(12) Si3 N4
SiO 2 SiO2 Al
(3) SiO2 SiO2 Photoresist
P-Si
Si3 N4
Arsenic implantation Al
3.10 Chapter Summary–A Device Fabrication Example SiO2
N+
SiO 2
(4)
SiO2 SiO2 P
P-Si Al
Metal (8) S iO2 S iO2
N+ (12) Si3 N4 Back side
etching SiO SiO2
(5)
2
P Al
N+ SiO2 SiO 2 metallization
P N+
2
P Dicing, wire bonding,
and packaging
(12) Si3 N4
Modern Semiconductor
Al Devices for Integrated Circuits (C. Hu) Slide 3-40
SiO2 SiO 2
N+