3­D ICs and Power Planning

Presented by
Dept. of Electronics Engineering Anant Kumar Singh
Pondicherry University Reg. No. : 18304002
M.Tech ECE, II yr.
CONTENTS
 Motivation
Objective
 Introduction
 Literature Review
 2D Vs 3D ICs
 Through silicon Vias(TSVs)
 Performance Characteristics
 Challenges in 3D ICs
Thermal Issues in3D ICs
 Conclusion
Proposed Work
 References 2
MOTIVATION
 Interconnect Limited VLSI Performance

 Physical Limitations Of Cu Interconnects

 System On Chip(SOC’s) Design

3
OBJECTIVE
o Improved interconnect performance,
o Increased transistor packing density,
o Reduced chip area,
o Reduced Power dissipation.

4
INTRODUCTION
 A 3D Integrated Circuit is
a chip that has active
electronic components
stacked on one or more
layers that are integrated
both vertically and
horizontally forming a
single circuit. A more
complex 3D-IC using
TSVs and six dice .

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INTRODUCTION
 • In a generic 3D IC structure, each die is stacked on top
of another and communicated by Through-Silicon Vias
(TSVs).
                   

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 LITERATURE REVIEW
Sl.
Journal & Year
No Title Author Inference
of Publication
.
 Three­
 This paper summarizes
Dimensional  Wen­Wei 
Nanoscale  various TSV fabrication
Integrated Circuit  Shen and  technologies for 3D
1 (3D IC) Key  Research 
Kuan­Neng  integration, including the
Technology:  Letters (2017) processes development, Cu
Chen
Through­Silicon  filling methods.
Via (TSV)
25th Annual 
   Dick James  SEMI Advanced 
 Moore’s law scaling dead 
3D ICs in the Real  Chipworks  Semiconductor 
2 by 2021, to be replaced 
World Inc. Ottawa,  Manufacturing 
Conference  by 3D integration
Canada 
(ASMC)(2014)
7
   The only way to bring 
down resistance and 
D.  capacitance is to use 
Shamiryan,  Materials  other metals (with lower 
Low­K dielectric 
T. Abell,  Today  resistivity) and 
3 materials
F. Iacopi1,  7(1); dielectrics (with lower 
and K.  (2004) dielectric constant) 
Maex1 instead of the 
conventional Al and 
SiO2.
  Replacing conventional 
SiO2 dielectric medium 
The Ultra­Low­k 
with the ultra­low­k 
Dielectric Materials for 
Peng Xu,  dielectric material for the 
Performance 
Zhongliang  Electronic coupled MLGNR 
Improvement in Coupled 
4 Pan ,  s8080849 interconnects has a 
Multilayer Graphene 
Zhenhua  (2019) greater performance 
Nanoribbon 
Tang advantage in terms of 
8
Interconnects
the crosstalk delay, noise 
output, and transfer gain 
 Tao Dong,
 
Zhaochu Ya  Flow boiling pressure drop 
   
ng,  in microchannel depends on 
Freon  R141b  flow  boiling   Springer­
5 Qincheng  both mass velocity and heat 
in  silicon  microchannel  Verlag 
Bi, Yulong  flux, which together 
heat  sinks:  experimental  (2007) determine the flow patterns
Zhang
investigation
 

  
P/G TSV planning for IR­ Shengchen  To minimize the IR­drop,
we co­optimize the locations, 
drop reduction in 3D­ICs g Wang, IEEE
6 sizes and the total number 
  Fardas  (2014)  of P/G TSVs simultaneously
Firouzi Using MILP Method.
 

9
  3D wiring changes alone 
  3D  integrated  circuits:  might provide a 5­30% 
Designing  in  a  new  device improvement, but 
Robert        
dimension:  Designer     IEEE combining different circuit 
7 Patti
track   (2012) types and using 3D 
  optimized architectures 
 
  could enable larger 
improvements.
  
 New device concepts,   This paper addresses 
transistor architectures  selected topics about recent 
and materials for high  developments in CMOS 
D. Esseni,
performance and energy   IEEE technologies evolving 
8  O. Badami
efficient CMOS circuits  (2018) towards 3D integrated 
  circuits and incorporating 
in the forthcoming era of 
3D integrated circuits innovative device concepts 
and ever new materials.

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    Embedded two 
 The work indicates that 
phase cooling of large  Mark  InterPACK/
this approach would be 
3D compatible chips  Schultz,  ICNMM201
9 well suited to
with radial channels Fanghao  5­48348
Yang, Evan  adequately cool stacked 3D 
(2015)
Colgan high power processor dies
 

  
Internation
  al Journal   In this paper, the 
PDN  Optimization  of  MALLIKAR of Advances  methodology for optimizing 
10 3D ICs using TSV  JUN.P.Y,  in Science  the number and position of 
Technology  Y.S.KUMA Engineerin both power bumps and power 
RSWAMY g and  TSVs is proposed.
Technology
(2014)
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2D VS 3D ICS

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THROUGH SILICON VIA(TSV)
 A Through­silicon via 
(TSV) or through­chip 
via is a vertical 
electrical connection 
(via) that passes 
completely through a 
silicon wafer or die.
 High speed and High 
Packaging density.
 Reduces interconnect 
Length.

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THROUGH SILICON VIA(TSV)

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PERFORMANCE CHARACTERISTICS
 Timing
 Energy Performance.

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TIMING
 In current technologies,
timing is interconnect
driven.
 Reducing interconnect
length in designs can
dramatically reduce RC
delays and increase chip
performance
 The graph below shows
the results of a reduction
in wire length due to 3D
routing
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ENERGY PERFORMANCE
 Energy dissipation decreases with the number of layers
used in the design
 Following graphs are based on the 3D tool MAGIC.

 MAGIC is an open source layout editor developed at UC

Berkeley.

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ENERGY PERFORMANCE

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CHALLENGES IN 3D CIRCUIT
 Thermal Issues in 3D-circuits
 EMI

 Reliability Issues

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THERMAL ISSUES IN 3D CIRCUITS
 Thermal Effects dramatically impact interconnect and
device reliability in 2D circuits
 Due to reduction in chip size of a 3D implementation,
3D circuits exhibit a sharp increase in power density
 Analysis of Thermal problems in 3D is necessary to
evaluate thermal robustness of different 3D technology
and design options.

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HEAT TRANSFER BY TSVS
 large die into smaller ones and stacking them decreases
thermal conductivity of the chip and temperature
increases
 (TSVs) which implement can help transferring heat to
the heat sink of the chip
 increasing number of layers from two to four increases
maximum temperature by 37.5%
 While increasing TSV count four times by double
increases maximum temperature by about 10% for six
layers 3D stack.
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FLOW BOILING METHOD
 Cooling stacked structures with multiple high power
layer utilizing single sided heat sink is difficult due to
the thermal resistance associated with multiple
intervening chip layers.
 A solution to this problem is coolant flowing
continuously between the stacked high power active
layers.

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JUNCTION TEMPERATURE VS HEAT FLUX

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CONCLUSION
 3D chip stacking with through silicon vias (TSVs) is one of
the major technologies for achieving higher silicon packaging
density and shorter interconnect.

 TSVs are high performance interconnect techniques used as

an alternative to wire-bond and flip chips to create 3D
packages and 3D integrated circuits.

TSVs are also helpful in heat transfer to microchannel heat

sinks leading to better performance of 3D ICs.

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PROPOSED WORK
 To introduce improved Power Planning in 3D ICs.

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REFERENCES 
 Aibin Y, Lau JH, Soon WH, Kumar A (2011) Fabrication
of high aspect ratio TSV and assembly with fine-pitch
low-cost solder micro bump for Si interposer technology
with high-density interconnects. IEEE Trans Compon
Packag Manuf Technol 1:1336–1344.
 Bagheri, A.; Ranjbar, M.; Haji-Nasiri, S.; Mirzakuchaki,
S. Crosstalk bandwidth and stability analysis in graphene
nanoribbon interconnects. Microelectron. Reliab.
2015,55, 1262–1268.

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REFERENCES
 Guo ZY (2000) Frontier of heat transfer—microscale
heat transfer. Adv Mech 30:1–6 (in Chinese).
 Morini GL (2004) Single-phase convective heat transfer
in microchannels: reviewof experimental results. Int J
Therm Sci 43:631–651.
 Haron, N. Z., and Hamdioui, S., "Why is CMOS scaling
coming to an END?," Proc. Design and Test Workshop,
2008. IDT 2008. 3rd International, pp. 98-103.

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THANK YOU

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