L7 Sequential Circuits

IEP on Synthesis of Digital Design 2007 Sequential Circuits
Sequential Circuits
S. Sundar Kumar Iyer
1
Acknowledgement
 Slides taken from
http://bwrc.eecs.berkeley.edu/IcBook/index.htm
which is the web-site of “Digital Integrated Circuit – A Design
Perspective” by Rabaey, Chandrakasan, Nicolic
2
Outline
 Background and naming conventions
 Timing constraints and stability issues
 MUX based latch and registers
 Cross-coupled pair
 Implementations
 Pseudo-static, C2MOS, TSPC, …
 Pipelining
 Schmitt Trigger and Multivibrators
3
Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Registers
Q D
CLK
2 storage mechanisms
• positive feedback
• charge-based
4
Naming Conventions
 Rabaey’s Convention
 a latch is level sensitive
 a register is edge-triggered
 There are many different naming
conventions
 For instance, many books call edge-
triggered elements flip-flops
 This leads to confusion however
5
Latch versus Register

 Latch  Register
stores data when stores data when
clock is low clock rises
D Q D Q
Clk Clk
Clk Clk
D D
Q Q
6
Latches
7
Latch-Based Design
• N latch is transparent • P latch is transparent
when f = 0 when f = 1
f
N P
Logic
Latch Latch
Logic
8
Timing Definitions
CLK
t Register
tsu thold D Q
D DATA CLK
STABLE t
tc 2 q
Q DATA
STABLE t
9
Characterizing Timing
tD 2 Q
D Q D Q
Clk Clk
tC 2 Q tC 2 Q
Register Latch
10
Maximum Clock Frequency

f
FF’s
LOGIC
tp,comb
Also:
tcdreg + tcdlogic > thold
tclk-Q + tp,comb + tsetup = T
tcd: contamination delay
= minimum delay
11
Positive Feedback: Bi-Stability
V o1 Vi2
1
o 1
o
V V
52
Vi
V i1 V o2
A
V i 2 = V o1
1
Vo
52 C
Vi
B
V i 1 = V o2
12
Meta-Stability
Gain should be larger than 1 in the transition region
13
Writing into a Static Latch

Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
Q D D
CLK
CLK
D
CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)
14
Mux-Based Latches
Negative latch Positive latch
(transparent when CLK= 0) (transparent when CLK= 1)
Q 0 Q
1
D 0 D 1
CLK CLK
Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

15
Mux-Based Latch
CLK
CLK
CLK
16
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only Non-overlapping clocks

17
Master-Slave (Edge-Triggered)
Register
Two opposite latches trigger on edge

Also called master-slave latch pair
18
Master-Slave Register
Multiplexer-based latch pair
I2 T2 I3 I5 T4 I6 Q
QM
D I1 T1 I4 T3
CLK
19
Clk-Q Delay
2.5
CLK
1.5
Volts
D
tc 2 q(lh) tc 2 q(hl)
Q
0.5
2 0.5
0 0.5 1 1.5 2 2.5
time, nsec
20
Setup Time
21
Reduced Clock Load

Master-Slave Register
CLK CLK
D T1 I1 T2 I3 Q
I2 I4
CLK CLK
22
Avoiding Clock Overlap

CLK X CLK
Q
A
D
B
CLK CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
Need to use non-overlapping clocks f1 and f2

23
Must be careful about limiting the non-overlapping period
Overpowering the Feedback Loop ─

Cross-Coupled Pairs
NOR-based set-reset
S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0
Forbidden State
24
Cross-Coupled NAND
Added clock
Cross-coupled NANDs VDD
S M2 M4
Q
Q
Q
Q CLK M6 M8 CLK
R M1 M3
S M5 M7 R
This is not used in datapaths any more,

but is a basic building memory cell
25
Sizing Issues
2.0 3
Q S
1.5
2 W = 0.5 m m
Q (Volts)
W = 0.6 m m
Volts
1.0
W = 0.7 m m
1
0.5 W = 0.8 m m
W = 0.9 m m
W = 1m m
0.0 0
2.0 2.5 3.0 3.5 4.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
W/L 5 and 6 time (ns)
(a) (b)
Output voltage dependence Transient response

on transistor width
26
Storage Mechanisms
Static Dynamic (charge-based)
CLK
CLK
D Q
Q
CLK
CLK
D
CLK
27
Making a Dynamic Latch Pseudo-Static
CLK
D D
CLK
28
Other Latches/Registers: C2MOS

VDD VDD
M2 M6
CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7
M1 M5
Master Stage Slave Stage
“Keepers” can be added to make circuit pseudo-static

Clocked CMOS 29
Insensitive to Clock-Overlap
VDD VDD VDD VDD
M2 M6 M2 M6
0 M4 0 M8
X X
D Q D Q
1 M3 1 M7
M1 M5 M1 M5
(a) (0-0) overlap (b) (1-1) overlap
May have dual edge registers

30
Other Latches/Registers: TSPC

VDD VDD VDD VDD
Out
In CLK CLK In CLK CLK
Out
Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)
True Single Phase Clocked Registers (avoids CLK’)
31
Including Logic in TSPC

VDD VDD VDD VDD
In1 In2
PUN
Q Q
In CLK CLK CLK CLK
PDN In1
In2
Example: logic inside the latch

AND latch
32
TSPC Register
VDD VDD VDD
CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8
CLK
M1 M4 M7
33
Sequential Circuits
Pulse-Triggered Latches
IEP on Synthesis of Digital Design 2007
An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q
Clk Clk Clk Clk

Clk
34
Pulsed Latches
VDD VDD
M3 M6 VDD
CLK
Q
D CLKG CLKG MP CLKG
M2 M5
X
MN
M1 M4
(a) register (b) glitch generation
CLK
CLKG
(c) glitch clock

35
Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 P3
x Q
M6
M3
D P2 M5
M2
M4
M1 CLKD
36
Hybrid Latch-FF Timing
37
Pipelining
REG
REG
a a
REG
REG
REG
REG
log Out CLK log Out
CLK
REG
REG
b CLK b CLK CLK CLK
CLK CLK
Reference Pipelined
38
Latch-Based Pipeline
39
Non-Bistable Sequential Circuits─

Schmitt Trigger
Vou t V OH
In Out
•VTC with hysteresis V OL
•Restores signal slopes
VM– VM+ Vi n
40
Noise Suppression using Schmitt

Trigger
41
CMOS Schmitt Trigger

VDD
M2 M4
Vin X Vout
M1 M3
Moves switching threshold

of the first inverter
42
Schmitt Trigger Simulated VTC
2.5 2.5
2.0 2.0
1.5 VM1 1.5
(V)
X1.0 VM2 (V)
x1.0
k=1
V V k=3
k=2
0.5 0.5
k=4
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.
43
CMOS Schmitt Trigger (2)

VDD
M4
M6
M3
In Out
M2
X M5
VDD
M1
44
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
45
Transition-Triggered Monostable
In
DELAY
Out
td td
46
Astable Multivibrators (Oscillators)

0 1 2 N-1
Ring Oscillator
simulated response of 5-stage oscillator
47
Differential Delay Element and VCO
V o2 V o1 v3
v1
in 1 in 2
v2
v
4
V ctrl
delay cell two stage VCO

3.0
V1 V2 V3 V4
2.5
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5 1.5 2.5 3.5
time (ns)
simulated waveforms of 2-stage VCO
48

L7 Sequential Circuits

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L7 Sequential Circuits

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IEP on Synthesis of Digital Design 2007 Sequential Circuits

S. Sundar Kumar Iyer

Latch versus Register

Maximum Clock Frequency

Positive Feedback: Bi-Stability

Gain should be larger than 1 in the transition region

Writing into a Static Latch

Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

NMOS only Non-overlapping clocks

Two opposite latches trigger on edge

Reduced Clock Load

Avoiding Clock Overlap

Need to use non-overlapping clocks f1 and f2

Overpowering the Feedback Loop ─

This is not used in datapaths any more,

Output voltage dependence Transient response

Making a Dynamic Latch Pseudo-Static

Other Latches/Registers: C2MOS

Master Stage Slave Stage

“Keepers” can be added to make circuit pseudo-static

(a) (0-0) overlap (b) (1-1) overlap

May have dual edge registers

Other Latches/Registers: TSPC

In CLK CLK In CLK CLK

Positive latch Negative latch

Including Logic in TSPC

In CLK CLK CLK CLK

Example: logic inside the latch

Clk Clk Clk Clk

(a) register (b) glitch generation

(c) glitch clock

Hybrid Latch-FF Timing

b CLK b CLK CLK CLK

Non-Bistable Sequential Circuits─

•VTC with hysteresis V OL

•Restores signal slopes

Noise Suppression using Schmitt

CMOS Schmitt Trigger

Moves switching threshold

Schmitt Trigger Simulated VTC

1.5 VM1 1.5

CMOS Schmitt Trigger (2)

Astable Multivibrators (Oscillators)

simulated response of 5-stage oscillator

Differential Delay Element and VCO

delay cell two stage VCO

simulated waveforms of 2-stage VCO

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