Module 4

Sequential Circuits
 Combinational circuits
• Circuit consisting of only logic gates
• Outputs are at all times dependent on the
combination of inputs
• Adders, Subtractors, MUX, DEMUX, Decoder,
Encoder
 Sequential circuits
• Outputs are dependent not only on the present
input conditions, but also depends upon past
outputs.
• Sequential circuits are made of combinational
circuits & memory elements
• The memory elements used are latches and flipflops
Sequential Circuits

Block Diagram
 Sequential Circuits
• Latches and Flip-flops are the basic building
blocks of most of the sequential circuits
• Latches watches its inputs continuously and
changes its outputs when input changes
• Flip-flops changes its outputs only when a clocking
signal is changing (triggered)
 Latch – non-clocked flipflops
• Circuit which is used to store information.
Information is 0 or 1.
• The information is locked or latched in the circuit,
hence the name latch
• Also known as non-clocked flipflops
 Latches
• S-R latch
• D latch
 S-R Latch
• Simplest latch
• 2 inputs, S & R
• 2 outputs, Q & Q’, output & its complement.
Logic symbol & Truth table
 Active high S-R latch
• Constructed using two cross coupled NOR gates.
• Output of each gate is connected to one of the
inputs of the other gate
Logic diagram of Active high S-R latch
S-R latch
 Active low S-R latch
• Constructed using two cross coupled NAND
gates.
• Output of each gate is connected to one of
the inputs of the other gate
Gated SR Latch
Gated D latch
Logic symbol of Gated D Latch

Truth Table
Input Enable Output
D EN Q

0 High 0
1 High 1
Flipflops
 Latch – Level triggered
• Latch stores the information until input
conditions changes
• Level triggered
• Asynchronous
D Latch – Level Triggering
 Flipflops
• Are synchronous bistable devices, known as
bistable multivibrator
• Synchronous means changes state only at a
specific point on a triggering input called the
clock (CLK), designated as a control input, C
• So changes in the output occur in
synchronization with the clock
• The difference between a latch and a flip-flop
is that a latch is asynchronous, and the
outputs can change as soon as the inputs do
(or at least after a small propagation delay). A
flip-flop, on the other hand, is edge-
triggered and only changes state when a
control signal goes from high to low or low to
high.
 Sequential Circuits

Block Diagram of Synchronous Clocked Sequential Circuits

• Flipflops are edge triggered
• An edge triggered FF changes state either at
the positive edge (rising edge (0 to 1)) or at
the negative edge (falling edge (1 to 0)) of the
clock pulse
• Edge Triggered
– Positive edge

Clock

– Negative edge

Clock

• Level Triggered

Clock
 Flip-Flops
• S-R FF (Set-Reset)
• J-K FF
• D FF (Data)
• T FF (Toggle)
• Master-Slave FFs
Positive Edge Triggered
S-R Flip-Flop
Characteristic Equation

Q(t + 1) = S + R’ Q
Truth Table/Function Table
Positive Edge Triggered S-R Flip-Flop
Internal circuitry
 Positive Edge Triggered
S-R Flip-Flop
Internal circuitry

• Transition or edge detector generates a positive

spike at the positive going edge of the clock pulse
• Steering gates ‘direct’ or ‘steer’ the narrow spike
either to G3 or to G4 depending on the state of the
inputs
Negative edge triggered SR flipflop
SR flip flop timing diagram
 Positive Edge – Triggered D Flip-
Flop
• The output will go to the same state that is present on D
input at the positive going transition of the clock pulse.
D (Data) Flip-Flop
Characteristic Equation

Truth Table
D (Data) Flip-Flop – Positive edge
triggered
• Timing Diagram
J-K Flip-Flops- Most widely used. Identical to
SR flipflop but no invalid state.
Characteristic Equation

Truth Table
J-K Flip-Flops
 J-K Flip-Flops

Data Output – Output –

Input Present State Next state Comments
JK Q QN+1
00 0 0 No Change
00 1 1
01 0 0 RESET
01 1 0
10 0 1 SET
10 1 1
11 0 1 Toggle
11 1 0
 J-K Flip-Flops
• Timing Diagram
T (TOGGLE) Flip-Flops
T (TOGGLE) Flip-Flops –
Internal Circuitry
T (TOGGLE) Flip-Flops
Characteristic Equation
 Preset and Clear
• Asynchronous Inputs
Preset and Clear
 Truth table & diagram

• The preset input drives the flip-flop to a

set state while the clear input drives it to
a reset state.
 Race Around Condition
• Happens in Level triggered J-K FF
• Race around condition occurs when both the input
are 1 (J =1 and K =1)
• If the width of the clock pulse is too long, the state of
the flip flop will output change or complements its
output from 1–>0 and 0–>1 and at the end of the
clock pulse, its state will be uncertain.
• This phenomenon is called toggling output or
uncontrolled changing or racing condition.
 Race Around Condition

Clock pulse
 Steps to avoid racing condition in
JK Flip flop:

• If the Clock On or High time is less than the

propagation delay of the flip flop then racing can
be avoided. This is done by using edge triggering
rather than level triggering.
• If the flip flop is made to toggle over one clock
period (Δt>tp) then racing can be avoided. This
introduced the concept of Master Slave JK flip flop.
Race Around Condition
Master Slave J-K FF
Master Slave J-K FF