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Memory

LECTURE-17-18

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Pipelining and Vector Processing 2 Pipelining

Memory Organization

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Memory Organization

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Memory Organization

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Memory Organization

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Memory Organization

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Memory Organization

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Memory Hierarchy

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Memory Hierarchy

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Memory Hierarchy

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Memory Hierarchy

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Main Memory

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Main Memory

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Main Memory

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Main Memory

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Main Memory: Memory address map

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Main Memory: Memory address map

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Main Memory: Memory address map

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Main Memory: Memory address map

Memory address map &

Connection to CPU

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Cache Memory

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Cache Memory

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Cache Memory

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Cache Memory

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Cache Memory

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Cache Memory – Associative Mapping

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Cache Memory – Associative Mapping

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Cache Memory – Associative Mapping

 The argument register A and key register K each have n bits, one for each bit
of a word.
 The match register M has m bits, one for each memory word.
 Only the three leftmost bits of A are compared with memory words because K
has 1's in these position.
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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Cache Memory – Direct Mapping

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Direct Mapped Cache Example

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Direct Mapped Cache Example

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Address Mapping using Pages

The table implementation of the address mapping is simplified if

the information in the address space and the memory space are
each divided into groups of fixed size.
The physical memory is broken down into groups of equal size
called blocks, which may range from 64 to 4096 words each.
The term page refers to groups of address space of the same size.
Consider a computer with an address space of 8K and a memory
space of 4K.
If we split each into groups of 1K words we obtain eight pages
and four blocks as shown in figure.
At any given time, up to four pages of address space may reside
in main memory in any one of the four blocks.

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Address Mapping using Pages

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Memory Table in Paged System

 The memory-page table consists of eight words, one for each page.
 The address in the page table denotes the page number and the
content of the word give the block number where that page is stored
in main memory.
 The table shows that pages 1, 2, 5, and 6 are now available in main
memory in blocks 3, 0, 1, and 2, respectively.
 A presence bit in each location indicates whether the page has been
transferred from auxiliary memory into main memory.
 A 0 in the presence bit indicates that this page is not available in main
memory.
 The CPU references a word in memory with a virtual address of 13
bits.
 The three high-order bits of the virtual address specify a page number and also
an address for the memory-page table.
 The three high-order bits of the virtual address specify a page number and also
an address for the memory-page table.
 The content of the word in the memory page table at the page number address is
read out into the memory table buffer register.
 If the presence bit is a 1, the block number thus read is transferred to the two
high order bits of the main memory address register.
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Memory Table in Paged System

 A read signal to
main memory
transfers the
content of the
word to the main
memory buffer
register ready to
be used by the
CPU.
 If the presence bit
in the word read
from the page
table is 0, it
signifies that the
content of the
word referenced
by the virtual
address does not
reside in main
memory.
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Logical to Physical Address Mapping

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