Seminar

A Versatile Control Scheme for a Dynamic Voltage Restorer for Power-Quality Improvement

Name :Mihir Gaglani

Roll No : 17EEE2008
M.Tech 1st Year PEPS
Contents :

 Introduction
 DVR, DVR Topologies and Control Strategies
 Control Schemes
 Controller Design
 Introduction
 What is Power Quality ?
 Importance behind a detailed study of Power Quality
 PQ disturbances.
 Dynamic Voltage Restorer (DVR)

 What is DVR?
 Principle behind DVR?
 DVR Topologies
 Control Strategy

Fig.1 System Configuration with a DVR

 Control Scheme

 Feed-Forward Control : To improve the transient stability. The effect of a

Disturbance input is to introduce error in system performance which needs to be kept
low, within acceptable limits. Here as the disturbance error can be predicted (computed
before hand), its effect can be eliminated with feed forward technique.

 Feedback Control along with Repetitive control : For Zero tracking error in steady
state.
 Schematic Representation of Single Phase DVR

Fig.2 SLD of a Single Phase DVR System

The KVL equation of the above SLD can be written as,

𝒅𝒊
𝒗(𝒕) = 𝒗𝒑𝒄𝒄 (𝒕) + 𝒖 𝒕 − 𝑹𝒊 𝒕 − 𝑳
𝒅𝒕
 Control Loop Scheme

Fig.3 Control Block

The Output equation Control Block Can be written as where,

𝑽 𝒔 = 𝑭 𝒔 𝑽 ∗ 𝒔 + 𝑭𝒘 𝒔 𝑽𝒑𝒄𝒄 𝒔 + 𝑭𝒊 (𝒔)𝑰(𝒔) 𝑷𝟏 𝒔 = 𝒆−𝒕𝒐𝒔

𝑷𝟐 𝒔 = 𝑳𝒔 + 𝑹
𝟏+𝑪 𝒔 𝑷𝟏 (𝒔) 𝟏−𝑷𝟏 (𝒔) −𝑷𝟐 (𝒔)
𝑭 𝒔 = 𝑭𝒘 𝒔 = 𝑭𝒊 𝒔 =
𝟏+𝑪 𝒔 𝑷𝟏 (𝒔) 𝟏+𝑪 𝒔 𝑷𝟏 (𝒔) 𝟏+𝑪 𝒔 𝑷𝟏 (𝒔)
Test Implementation Schematic

Fig.4 Test Implementation of DVR System

Control Schematic

Fig.5 Phase A Control Circuit

Fig.6 Phase B Control Circuit

Control Schematic

Fig.7 Phase C Control Circuit

PWM Technique

Fig.8 Sinusoidal PWM Generation

 Observations
Corresponding to interval 0≤t<0.2

Fig. 9 Line to line voltage at PCC

Fig. 10 Line to line voltage across Sensitive Load

 Observations
 Control Voltage injected by the DVR

Fig.11 Voltage injected by Phase A of DVR ( Control Output )

Fig.12 Voltage injected by Phase B of DVR ( Control Output )

Fig.13 Voltage injected by Phase C of DVR ( Control Output )

 Observations ( 0.2 ≤ t < 0.28)

Fig.14 Sensitive Load Line-To-Line Voltage Vab (V)

Fig.15 Sensitive Load Line-To-Line Voltage Vbc (V)

Fig.16 Sensitive Load Line-To-Line Voltage Vac (V)

 Observations

Fig.17 THD in the Sensitive load during the duration ( 0.2 ≤ t < 0.28) sec
Thank you