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Vdocuments - MX - Chapter 5 Ee603
Vdocuments - MX - Chapter 5 Ee603
Graph for
IDSn vs VDSn ?
STATIC CMOS INVERTER
• CMOS Inverter Load lines
– Load-lines curve of PMOS are obtained by
mirroring x-axis and horizontal shift over VDD.
STATIC CMOS INVERTER
• CMOS Inverter Load lines
STATIC CMOS INVERTER
• CMOS Inverter Load lines
– For DC operating point to be valid :
• current for NMOS and PMOS must be equal.
• DC point must be located at the intersection of
corresponding load lines.
– Intersection : (Vin = 0, 0.5, 1, 1.5, 2 and
2.5V) Observation : all operation points are at
high or low output level.
STATIC CMOS INVERTER
• CMOS Inverter Load lines
STATIC CMOS INVERTER
STATIC CMOS INVERTER
• CMOS Inverter Voltage Transfer
Characteristic
– show very narrow transition zone.
– A small change in input voltage results in a
large output variation.
STATIC CMOS INVERTER
• Switch model of dynamic behavior of
static CMOS inverter:
Back to Slide 40
STATIC CMOS INVERTER
• Decreasing RP or Rn
can be achieved by
increasing ratio.
• Small transistor
sizing give better
performance of CMOS
inverter.
STATIC CMOS INVERTER
• Robustness of CMOS Inverter:
1. Switching Threshold
2. Noise margin
ROBUSTNESS OF CMOS
INVERTER
1. Switching Threshold
— Switching Threshold, VM is defined as point
where Vin = Vout.
— PMOS and NMOS are saturated since VDS =
VGS.
ROBUSTNESS OF CMOS
INVERTER
— An analytical expression for VM is obtained
by equating the currents through the
transistors.
Go to Slide 23
DYNAMIC BEHAVIOR OF
CMOS INVERTER
• This figure shows the schematic of
cascaded inverter pair. It includes all the
capacitances influencing Vout. CL breaks
down into Cgd12, Cdb1, Cdb2.
DYNAMIC BEHAVIOR OF
CMOS INVERTER
• Gate-Drain Capacitance, Cgd12.
– M1 and M2 are either in cut-off or in the
saturation mode. This contribute to Cgd12
(overlap capacitances of M1 and M2).
– Using lumped capacitor model (getting CL),
require this gate-drain capacitor replaced by
a capacitance-to-ground. Miller effect.
DYNAMIC BEHAVIOR OF
CMOS INVERTER
• Miller Effect