Basic Concepts

• A memory device can be viewed as a

single column table. Memory Address Memory
– Table index (row number) refers to Binary Hex Contents
the address of the memory. 00-0000-0000 000 10011001
– Table entries refer to the memory 00-0000-0001 001 00111000
contents or data.
00-0000-0010 002 11001001
– Each table entry is referred as a
memory location or as a word. 00-0000-0011 003 00111011
• Both the memory address and the
memory contents are binary numbers,
expressed in most cases in Hex format.
• The size of a memory device is 11-1111-1100 3FC 01101000
specified as the number of memory 11-1111-1101 3FD 10111001
locations X width or word size (in bits). 11-1111-1110 3FE 00110100
– For example a 1K X 8 memory 11-1111-1111 3FF 00011000
device has 1024 memory locations,
with a width of 8 bits.
1024 X 8 (or 1KX8) Memory

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 Address Lines

• A memory device or memory chip must have

three types of lines or connections: Address,
Data, and Control.
• Address Lines: The input lines that select a
Y00 Location 000
memory location within the memory device. Y01 Location 001
– Decoders are used, inside the memory chip, to Y02 Location 002
select a specific location A00 Y03 Location 003
– The number of address pins on a memory chip A01
specifies the number of memory locations.
• If a memory chip has 13 address pins An-2
(A0..A12), then it has: An-1 YFC Location 0FC
213 = 23 X 210 = 8K locations. YFD Location 0FD
YFE Location 0FE
• If a memory chip has 4K locations, then it
YFF Location 0FF
should have N pins:
2N = 4K = 22 X 210 = 212  N=12 address
pins (A0..A11)

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 Data Lines
• Data Connections: All memory devices have a set of data output pins (for ROM
devices), or input/output pins (for RAM devices).
– Most RAM chips have common bi-directional I/O connections.
– Most memory devices have 1, 8 or 16 data lines.

Data Input Lines

(DI0..DIn-1)
k- address lines k- address lines
(A0..Am-1 ) 2m words (A0..A m-1 ) 2m words
k- address lines
(A0..A m-1 ) 2m words
Read/Write (R/W) n-bits per Output Enable (OE) n-bits per
Read (RD) n-bits per word word
Chip Select (CS) Chip Select (CS)
Write (WR) word
Chip Select (CS)
Data Output Lines
Data Input/Output (D0..Dn-1 )
Data Output Lines Lines (D0..Dn-1 )
(DO0..DOn-1 ) (2m X n) ROM with only O/P Data
(2m X n) RAM with common I/P
(2m X n) RAM with separate I/P lines
and O/P Data lines
and O/P Data lines

3
 Control Lines
• Enable Connections:
– All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
• If a device is not selected or enabled then no data can be read from, or
written into it.
• The CS or CE input is usually controlled by the microprocessor through the
higher address lines via an address decoding circuit.
• Control Connections:
– RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
• Some RAM chips have a common Read/ Write (R/W) signal.
– ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
• In most real ROM devices the Read signal is called the Output Enable
(OE) signal.

4
 Memory Read Operations
• A memory read operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location to be read (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be read (Step 1a), while the rest point to the required memory location within the
memory device.
– The processor activates the Read (RD) signal (Step 2).
• The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
– The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock T1 T2 T3

Address Bus Valid Address

Chip Enable

Read (RD)

Data Bus Invalid Data Valid Data

Step 1a
Step 2 Step 3 Step 4
Step 1

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 Memory Write Operations
• A memory write operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be written (Step 1a), while the rest point to the required memory location within
the memory device.
– The processor loads on the data bus the data to be written (Step 2).
– The processor activates the Write (WR) signal (Step 3).
• The data at the data bus is stored in the memory location specified by the address
bus (Step 4).
Clock T1 T2 T3

Address Bus Valid Address

Data Bus Valid Data

Chip Enable

Write (WR)
Step 2
Step 1
Step 4
Step 1a Step 3

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 Types of semiconductor memory devices: EPROM
• EPROM is a type of ROM that can be erased and re-programmed. There are two types
of EPROMs: the ultra-violet (UV-EPROMs) and the electrically erasable (EEPROMs)
often called the flash memory.
• UV-EPROMs are erased by inserting the device in ultra violet light and programmed
using a special EPROM programmer. UV-EPROMs need to be removed from the PCB
in order to erased and programmed.
• The most common family of EPROMs is the 27XXX series, or the CMOS 27CXXX
where XXX indicates the memory capacity in Kbits. Some members of this family are
the following:
2716/27C16 (2Kx8) 2732/27C16 (4Kx8)
2764/27C64 (8Kx8) 27128/27C128 (16Kx8)
27256/27C256 (32Kx8) 27512/27C512 (64Kx8)
27010/27C010 (128Kx8) 271024/27C1024 (64Kx16)
27020/27C020 (256Kx8) 272048/27C2048 (128Kx16)
27040/27C040 (512Kx8) 274096/27C4096 (256Kx16)

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 Types of semiconductor memory devices: Static RAM
• Static RAM (also called SRAM)devices retain their data for as long as the DC power is
applied.
• The most common family of SRAM are the 61XXX, 62XXX or the CMOS 62CXXX
series, where XXX indicates the memory capacity in Kbits. Some members of this
family are the following:
6116/6216 (2Kx8) 6164/6264 (8Kx8)
61256/62256 (32Kx8) 611024/621024 (128Kx8)
• These series of SRAM devices are pin compatible with the 27XXX series of EPROMs,
with the difference that the WR signal is replaced by the programming voltage pin
(Vpp) on the EPROM. This allows a single socket on the PCB hold either a SRAM,
during system development, or an EPROM, after the operation of the program is
verified to be the expected one.
• Static RAM is fast with access times much less than 100ns. SRAM chips with access
times less than 10ns are often used as cache memory in computers.
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 Semiconductor Memory Expansion
• The size of memory devices is usually less than the memory requirements of a computer system.
• In all computers, more than one memory devices are combined together to form the main
memory of the system.
• Any computer must have at least one ROM chip and one RAM chip.
• Word size memory expansion:
– Most memory devices have a word size (number of data lines) of 8 or 16 bits.
– The word size of today’s microprocessors is 32 bits (80386, 80486) or 64 bits
(Pentium)
• Address size memory expansion:
– The size of common memory chips is usually less or in the order of 256M-byte.
– Most personal computers have more than 2 Gbytes of RAM.
– Workstations and other high throughput computers have more than 4Gbytes of RAM.

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 Memory Address Size Expansion

• More than one memory devices can be used to expand the number of memory
locations on the system.
• To expand the word size do the following:
– Determine the number of memory chips required, by dividing the required
memory size with the size of the memory devices to be used.
– Connect the data lines of each memory chip in parallel on the data lines of
the processor.
– Connect the address lines of each memory chip in parallel with the low
address lines of the processor.
– Connect the CS lines of each memory device with the high address lines of
the processor through an address decoding circuit..
– Connect together all WR and all RD lines of each memory device.

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 Address Size Expansion: (32X4 RAM module using 8X4 RAM chips)

D0
D1
D2
D3
RAM1 D3 D0 RAM2 D3 D0 RAM3 D3 D0 RAM4 D3 D0
0 0 0 0
1 1 1 1
2 2 2 2
A0 3 A0 3 A0 3 A0 3
A1 4 A1 4 A1 4 A1 4
A2 5 A2 5 A2 5 A2 5
6 6 6 6
7 7 7 7
RD WR CS RD WR CS RD WR CS RD WR CS
RD
WR
A0
A1
A2
A3 A Y0
A4 B Y1
A5 Y2
CS
A6 Y3
Address 2X4 DEC.
Selection

11
 Memory Maps
• Tables that show the addresses occupied by each memory device in a system.

• In the previous example it is assumed A5 A5 A5 A5

that the processor has only 7 address A6 A6 A6 A6
line, thus it can address 128 memory
00 - 07 RAM 1
locations.
08 - 0F RAM 2 Not Not Not
• The size of the RAM memory 10 - 17 RAM 3 Used
00 - 1F
Used 00 - 1F Used
00 - 1F
module is 32 bytes, thus the module 18 - 1F RAM 4
can be mapped to occupy one out of 20 - 27 RAM 1
the four available memory blocks in 28 - 2F RAM 2
Not Not
the memory map. 20 - 3F
Used 30 - 37 RAM 3 20 - 3F
Not 20 - 3F
Used
Used
• The memory block occupied by the 38 - 3F RAM 4
memory module depends on the 40 - 47 RAM 1
connection of the address selection Not Not 48 - 4F RAM 2 Not
40 - 5F 40 - 5F 40 - 5F
Used Used Used
circuit (AND gate) that enables the 50 - 57 RAM 3

decoder. 58 - 5F RAM 4
60 - 67 RAM 1
60 - 7F Not 60 - 7F Not Not 68 - 6F RAM 2
60 - 7F
Used Used Used 70 - 77 RAM 3
78 - 7F RAM 4

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 Effect of the Address Selection Circuit
• The memory block occupied by the memory module depends on the connection of the
address selection circuit (AND gate) that enables the decoder.
• Two address lines are used to control the address selection circuit, thus the circuit can be
configured to occupy four different areas in the address space.

Address Selection A5 Address Selection A5 Address Selection A5 Address Selection A5

Circuit A6 Circuit A6 Circuit A6 Circuit A6

A6 A5 A4 A3 A2 A1 A0 Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map

0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00 Not 0 0 0 0 0 0 0 00 Not 0 0 0 0 0 0 0 00 Not
RAM1 Used
0 0 0 0 1 1 1 07 0 0 1 1 1 1 1 1F Used 0 1 1 1 1 1 1 3F 1 0 1 1 1 1 1 5F Used
0 0 0 1 0 0 0 08 0 1 0 0 0 0 0 20 1 0 0 0 0 0 0 40 1 1 0 0 0 0 0 60
RAM2 RAM1 RAM1 RAM1
0 0 0 1 1 1 1 0F 0 1 0 0 1 1 1 27 1 0 0 0 1 1 1 47 1 1 0 0 1 1 1 67
0 0 1 0 0 0 0 10 0 1 0 1 0 0 0 28 1 0 0 1 0 0 0 48 1 1 0 1 0 0 0 68
RAM3 RAM2 RAM2 RAM2
0 0 1 0 1 1 1 17 0 1 0 1 1 1 1 2F 1 0 0 1 1 1 1 4F 1 1 0 1 1 1 1 6F
0 0 1 1 0 0 0 18 0 1 1 0 0 0 0 30 1 0 1 0 0 0 0 50 1 1 1 0 0 0 0 70
RAM4 RAM3 RAM3 RAM3
0 0 1 1 1 1 1 1F 0 1 1 0 1 1 1 37 1 0 1 0 1 1 1 57 1 1 1 0 1 1 1 77
0 1 0 0 0 0 0 20 Not 0 1 1 1 0 0 0 38 1 0 1 1 0 0 0 58 1 1 1 1 0 0 0 78
RAM4 RAM4 RAM4
1 1 1 1 1 1 1 7F Used 0 1 1 1 1 1 1 3F 1 0 1 1 1 1 1 5F 1 1 1 1 1 1 1 7F
1 0 0 0 0 0 0 40 Not 1 1 0 0 0 0 0 60 Not
1 1 1 1 1 1 1 7F Used 1 1 1 1 1 1 1 7F Used

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Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)

D3 D0 D3 D0 D3 D0 D3 D0
D3
8x4 RAM 1 8x4 RAM 2 8x4 RAM 3 8x4 RAM 4
A0 A0 A0 A0
D0
A2 A2 A2 A2

RD WR CS RD WR CS RD WR CS RD WR CS

RD
WR

A0

2X4 DEC.
A2
A3 A Y0
A4 B Y1
A5 Y2
A6 CS Y3
A7

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 Memory Map for previous example.
• There are three address lines connected on the address selection circuit. Thus there can
be eight different memory map configurations.
• Three possible memory map configurations are shown below.

Address Selection A5 Address Selection A5 Address Selection A5

Circuit
A6 Circuit
A6 Circuit
A6
A7 A7 A7

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map

0 0 0 0 0 0 0 0 00
RAM1
0 0 0 0 0 1 1 1 07
0 0 0 0 1 0 0 0 08
RAM2
0 0 0 0 1 1 1 1 0F
0 0 0 1 0 0 0 0 10
RAM3
0 0 0 1 0 1 1 1 17
0 0 0 1 1 0 0 0 18
RAM4
0 0 0 1 1 1 1 1 1F
0 0 1 0 0 0 0 0 20 Not
Used
1 1 1 1 1 1 1 1 FF
0 0 0 0 0 0 0 0 00 Not
Used
1 0 0 1 1 1 1 1 9F
1 0 1 0 0 0 0 0 A0
RAM1
1 0 1 0 0 1 1 1 A7
1 0 1 0 1 0 0 0 A8
RAM2
1 0 1 0 1 1 1 1 AF
1 0 1 1 0 0 0 0 B0
RAM3
1 0 1 1 0 1 1 1 B7
1 0 1 1 1 0 0 0 B8
RAM4
1 0 1 1 1 1 1 1 BF
1 1 0 0 0 0 0 0 C0 Not
1 1 1 1 1 1 1 1 FF Used
0 0 0 0 0 0 0 0 00 Not
Used
1 1 0 1 1 1 1 1 DF
1 1 1 0 0 0 0 0 E0
RAM1
1 1 1 0 0 1 1 1 E7
1 1 1 0 1 0 0 0 E8
RAM2
1 1 1 0 1 1 1 1 EF
1 1 1 1 0 0 0 0 F0
RAM3
1 1 1 1 0 1 1 1 F7
1 1 1 1 1 0 0 0 F8
RAM4
1 1 1 1 1 1 1 1 FF

15
 Design Example:
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on
an 8-bit processor with a 16-bit address bus, and occupy the address range starting from the
address A000. Show the circuit and the memory map.

• Number of memory devices needed = 8K/2K Starting Address = A000 = 1010-0000-0000-0000

==> A15 = 1, A14 = 0 and A13 = 1
=4 A13
• Decoder needed = 2X4 Address Selection Circuit A14
A15
• Number of address lines on each 2KX8 A15 A14 A13 A12 A11 A10 A0 Mem. Map
memory chip = 11 0 0 0 0 0 0 0 0000 Not
2m = 2K = 21 x 210 = 211  (A0..A10) 1 0 0 1 1 1 1 9FFF Used

• Decoder needed = 2X4 1 0 1 0 0 0 0 A000

RAM1
1 0 1 0 0 1 1 A7FF
 2 address lines are needed for the decoder. 1 0 1 0 1 0 0 A800
 (A11..A12) 1 0 1 0 1 1 1 AFFF
RAM2

• Number of address lines needed for the 1 0 1 1 0 0 0 B000

RAM3
address selection circuit 1 0 1 1 0 1 1 B7FF

= 16 - 11 - 2 = 3  (A13, A14 A15) 1 0 1 1 1 0 0 B800

RAM4
1 0 1 1 1 1 1 BFFF
1 1 0 0 0 0 0 C000 Not
1 1 1 1 1 1 1 FFFF Used

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 Circuit Diagram

D7
D0 D7 D0 D7 D0 D7 D0 D7

2Kx8 RAM 2Kx8 RAM 2Kx8 RAM 2Kx8 RAM

D0 A0 A0 A0 A0

A10 A10 A10 A10

RD WR CS RD WR CS RD WR CS RD WR CS

RD
WR

A0
2X4 DEC.
A11
A Y0
A12
B Y1
A13
Y2
A14
CS Y3
A15 A15

17