ARTIFICIAL INTELLIGENCE AND

INDUSTRY 4.0
RESEARCH PAPER PRESENTATION:

Title:
Green and Sustainable FPGA component
for Future with AI.

Authored By:
Nidhi B. Satija
Sandhya Mishra
 OBJECTIVE OF THE RESEARCH :
 From smart homes to self-driving cars to medical devices, artificial intelligence (AI) have been center stage.

 The continued development of the internet of things and connected devices are driving shifts in systems architectures and
new applications.

 Designers building computing solutions on the edge are challenged to meet new requirements that are flexible, low-power,
small-form-factor, and low-cost, all without compromising power and performance.

 Designers need FPGAs that allow them to build compact AI devices that deliver high performance without violating
footprint or thermal management constraints, and offer maximum design flexibility and support a wide range of I/O
interfaces in a market.

The Main objective is to design an AI [FPGA] based component that would be essential
for Industry 4.0
 ARTIFICIAL
INTELLIGENCE
 FPGA
Methodology:
 The Xilinx FPGA device methodology
allows to achieve the optimality of device
and design characteristics, such as:

• Routing Utilization
• Design Performance
• Power Consumption

 This methodology also allows to achieve

efficiencies in:

• Software runtime
• Debugging capability
• Portability
 64-bit FPGA Counter :
The sequential logic device, formed with the fabrication of different logic gates is Counter.
It is the Difference marker deciding the time lagging and leading of the hardware.

Top Level of schematic of 64-bit The Behavioural simulation process

Counter
 Results and Observations:
For our component we have used 5G frequency which ranges from 30 GHz to 70 GHz
with the combination of constant voltage 0.970 and enhanced by using I/O standards
of 15 series with Virtex -7 Series family.

Power calculated by applying LVCMOS 15 at

voltage 0.970 Volt which reduced total power
consumption by 54.79%.
Power calculated by applying LVDCI_ 15 at Power calculated by applying SSTL_15 at
voltage 0.970 Volt which reduced total power voltage 0.970 Volt which reduced total power
consumption by 53.76%. consumption by 53.76%.
 Conclusion:
In our experiment we have designed AI
efficient and sustainable FPGA based 64-bit
counter and calculated the total power
consumption of the device. We have Calculated
total power by considering clock, signal, IO
and Leakage power as our parameter. Here,
our component is efficient for 5G Frequency
range by applying the constant voltage of 0.970
on the IO Standards of 15 series. Working with
SSTL15,we reduce the power consumption by
48.41% , by using LVDCI_15 we get 53.76%
power reduction and the most significant and
efficient result is 54.79% by using LVCMOS 15
IO Standard.
 Future Scope:
In this work, Counter Design is implemented on
Virtex-7, we can redesign this component with
the new family of FPGA like Kintex7 & Artix7
and computing power consumption by using
different IO Standard. This AI efficient counter
can be design further by using frequency range
for 7G and 9G technology and hence this FPGA
based counter can increase the sustainability of
the AI based components and