A Uni-bus Data Path

Implementation for the SRC

• The Data Path

• A Uni-bus Data Path
• Timing step Generator
Review
 CS501
Advanced Computer
Architecture

Lecture12

Dr.Noor Muhammad Sheikh

 Data
Path

CONTROL
 1. The Data Path
• The data path is the arithmetic
organ of the von Neumann
organization
• It consists of registers, internal
buses, arithmetic units and
shifters
 2. A Unibus Data Path Implementation
31 0 <31..0>
R0
R1 32 lines
General
purpose
registers
(32-bits each) A

R31 ADD
ALSU SUB

…
31 0
PC SHL
IR
MAR
MBR
C
Other
To external ALSU
CPU bus functions
Internal processor bus
 3. Timing Step Generator

• In the next few slides, we will assume

that there exists a “timing step
generator” which provides mutually
exclusive and sequential timing
intervals
• These intervals will be called T0, T1,
T2, …..
 Timing Step Generator
A possible implementation
A 3-to-8 decoder
T0

T1
T2
0
A 3-bit T3
binary counter 1
T4
2
T5

T6

T7
clear
Timing Step Generator
Waveforms

Eight
mutually
exclusive
time
steps
Timing Step Generator
Waveforms

If more time steps are

required, then a counter
with more bits and a larger
decoder can be used, eg.,
a 4-bit counter along with a
4-to-16 decoder can
produce up to 16 time
steps
 Structural RTL

• Describes how an operation is

performed using a particular
hardware implementation
 Structural RTL for the sub instruction
Syntax: sub ra, rb, rc

Step RTL
T0 MAR PC, C PC + 4;

Instruction T1 MBR M[MAR], PC C;

Fetch
T2 IR MBR;

T3 A R[rb];

Instruction T4 C A - R[rc];
Execute
T5 R[ra] C;

At the end of each sequence, the timing step generator is initialized to T0

 A Unibus Data Path Implementation
31 0
de <31..0>
i
sl
R0
R1 us 32 lines
General io
e
purpose v
pr
registers
om
r A
l l f(32-bits each)
ca
Re
R31 ADD
ALSU SUB

…
31 0
PC SHL
IR
MAR
MBR
C
Other
To external ALSU
CPU bus functions
Internal processor bus
 ALSU Functions Needed
ALSU Needed for the following
assuming Function instructions/operations
a barrel
ADD add, addi, address calculation for disp and rel
shifter
with five SUB sub
n<4..0> NEG neg; applies to the B input of the ALSU
signals
AND and, andi
available
as well OR or, ori
NOT not; applies to the B input of the ALSU
SHL shl
Use uppercase for control
SHR shr
signals, because lowercase
SHC shc was used for mnemonics
SHRA shra
C=B to load from the bus directly into C
INC4 to increment the PC by 4; applies to the B input;
 A Unibus Data Path Implementation
31 0
e <31..0>
R0 l id
s
R1 Question: s
General iou 32 lines
e
purpose v
Whatpr will be the implications if the
registers
om
connection between registerAC and the
f r
(32-bits each)
all internal processor bus is bi-directional ?
ec
R (one would like to have such a
R31 ADD
connection to avoid loading C through
ALSU SUB

…
31 0
the ALSU) SHL
PC
IR
MAR
MBR
C
Other
To external ALSU
CPU bus functions
Internal processor bus
Structural RTL for the add instruction
Syntax: add ra, rb, rc

Step RTL
T0-T2 Instruction fetch

T3 A R[rb];

T4 C A + R[rc];

T5 R[ra] C;

other instructions that will have similar tables are:

and, or, sub
Structural RTL for the not instruction

Syntax: not ra, rb

Step RTL
T0-T2 Instruction fetch

T3 C !(R[rb]);

T4 R[ra] C;

another instruction that will have similar table is:

neg
Structural RTL for the addi instruction
Syntax: addi ra, rb, c2

Step RTL
T0-T2 Instruction fetch

T3 A R[rb];

T4 C A + c2(sign extend);

T5 R[ra] C;

Sign extension for 17-bit c2 is the same as : (15αIR<16> ©IR<16..0>)

Sign extension for 22-bit c1 is the same as : (10αIR<21> ©IR<21..0>)

other instructions that will have similar tables are:

andi, ori
 RTL for the ld and st instructions
Syntax: ld ra, c2(rb) Syntax: st ra, c2(rb)

Step RTL for Id RTL for st

T0-T2 Instruction fetch Instruction fetch
T3 A ((rb = 0) : 0, (rb ≠ 0): R[rb]); A ((rb = 0): 0, (rb ≠ 0): R[rb]);

T4 C A + (15αIR<16> ©IR<16..0>); C A + (15αIR<16> ©IR<16..0>);

T5 MAR C; MAR C;

T6 MBR M[MAR]; MBR R [ra];

T7 R[ra] MBR; M[MAR] MBR;

ld and st are the same up to step T5

sign Note that (15αIR<16> ©IR<16..0>) is the
extension
same as (16αIR<16> ©IR<15..0>)