K.L.E.

Society’s
K. L. E. INSTITUTE OF TECHNOLOGY
HUBBALLI – 580 030.

Dept. of Electronics and Communication Engineering

Presentation on
RTL Design And Design Verification

Guide: Student Name:

Mr. Vishwas Patil Saumya Rane
2KE16EC115

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 Contents
1. Introduction
2. Objectives
3. Company Profile
4. Duration spent and Activities Performed
5. Projects Implemented
6. Methodology
7. Experiences/Lesson learnt in the company
8. Conclusion

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 1. Introduction

Fig. 1 A Conceptual Design Flow From Specifications To Final Product

[3]
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 1. Introduction….
• RTL Design: The functional design is the initial process of
deriving a potential and realizable solution from the design
specifications and requirements. The architectural descriptions
are further refined memory element and functional components
of each model are designed using a Hardware Description
Languages (HDL).
• Design Verification: verification is functional validation. The
functional model of a design is simulated with meaningful input
stimuli and the output is checked for the expected behavior.

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 2. Objectives

• To explore the current technological developments relevant to

the area of RTL verification.
• To apply the Technical knowledge in real industrial situations.
• To learn the basics of linux operating system.

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 3. Company Profile
• Semi-ksha Semiconductors Private Limited Located at KLE
technological university campus Hubballi, Dharwad .
• The motto of semi-ksha semiconductors is to bring up best out of Design
Verification in the current Technology Transformation in the field of
VLSI/Semiconductor.
• The mission of Semi-ksha semiconductors is to Groom up fresh graduates
for semiconductor industry.

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4.Duration spent and Activities Performed
• Duration Spent: 4 weeks [8th July 2019 – 5th August 2019 ]
• Activities Performed:
Week 1 :
• Introduction about the Semi-ksha Semiconductors.
• Introduction to Cadence and Linux Operating System.
• Introduction to RTL Design and RTL Verification covered.
Week 2:
• Design specification, Analysis of specification, Feature
extraction and the Test strategy planning, the Test bench
architecture.
• Seminar on System on Chip and Verification by Industry
Expert.
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 4. Activities Performed....
Week 3:
• Concepts of System Verilog was introduced.
• There was Hands-on training for all the simulation programs.
The errors which occurred during simulation of the programs
were debugged with the proper knowledge about them.
Week 4:
• We were made to work with the testbenches of Memory and
Adder.
• Scoreboard, monitor, test, testcases, program, top, driver,
generator, transaction, transaction class codes was simulated and
their output were analyzed.

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 5. Projects Implemented
• Memory Design and RTL verification: This project mainly
focuses on verifying the important features of Memory
model shown in fig.2 using System Verilog.

Fig. 2 Memory Model Specification

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 5. Project Implemented…
• The memory chip's support circuitry allows the user to read the data stored in the
memory's cells, and write data to the cells.
• This circuitry generally includes:
1. Address logic to select rows and columns.
2. Translation logic that "reads" the data in a cell and sends that data to the data I/O.
3. Write logic that takes the user data applied at the input and stores it in a memory
cell.
4. Output enable logic to prevent data from appearing at the outputs unless
specifically desired.
5. Internal counters and registers to keep track of burst address sequences, pipelined
data, and other control functions on the chip.
6. Clock circuitry to control the timing of the read and write operations and all of
their variations.

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 6. Methodology
• The steps involved in the verification process are,
1. Creation of Verification plan:
The Verification Plan is the focal point for defining exactly
what needs to be tested, and drives the coverage criteria.
2. Test bench Architecture:
Testbench Architecture is used to check the functional
correctness of the Design Under Test (DUT) by generating and
driving a predefined input sequence to a design, capturing the
design output and comparing with respect to expected output .
3. Writing testbench:
Each feature of the design should be tested to ensure that the

unexpected bugs have not been introduced into the design.

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 6. Methodology…

Fig.3 Testbench Architecture

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 7. Experience/Lesson Learnt

• Execute the verification test Plan by developing stimulus using

system verilog .
• Worked closely with RTL designers to develop verification
Plan.
• Excellent testing and hands on Experience.
• Team work and career alternatives.
• Developing work habits and attitudes necessary for job.
• Actively participated in the events conducted during internship
period.`

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 8. Conclusion

• Verification occurs throughout the design flow and should

occur at various levels of integration.
• Verification approaches are testing, design reviews/code
inspections, prototype/emulation, requirements tracing, and
formal verification.

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 Bibliography
[1] TD Hamalainen, Implementation of SystemVerilog and UVM Training
Tampere University of Technology Master of Science Thesis, 2017
[2] Chris Spear Synopsys, Inc. SystemVerilog for Verification: A Guide to
Learning the Testbench Language Features. Marlboro, MA: Springer,
2006.
[3] Web.eecs.umich.edu/research/thesis/thesis2.pdf
[4] https://www.verificationguide.com/p/systemverilog-testbench-example-
01.html

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Thank you

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