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Introduction

 Power dissipation of digital systems have been continued


to be focused on hardware design.

 The manner in which software uses and directs the


hardware can have a substantial impact on the power
dissipation.

 No efficient and accurate tools to estimate overall effect of


software design on power dissipation.

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Sources of SPD
 Memory system takes 1/10t to 1/4th fraction of the power
budget.
 More sensitive DSP power applications such as
video processing.
 System buses with large switching activity.
 Data paths in ALUs and FPUs.
 Control logic and clock distribution.
 Program’s energy dissipation is proportional to
the number of execution cycles of the program.

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Software Power Estimation
 Lower level approach - Use gate level simulation
and power estimation tools.
 Higher level approach – Estimate power based
on frequency of execution of instruction sequence.
 Gate level Power Estimation
> Most accurate method available assuming detailed gate
level description is available.
> Too slow for low power optimization, but more important
in evaluating the power dissipation behavior of a
processor design.
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Software Power Estimation contd...

Architectural Level Power Estimation


> Less precise but much faster
>Is implemented in a Power Estimation Simulator called
ESP(Early design Stage Power and performance
simulator).
Bus Switching Activity
> Bus activity is assumed to be representative.
> Requires knowledge about architecture of processor, op-
codes for instruction set, input data to a program, etc.

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Software Power Estimation contd...

Instruction Level Power Analysis


With the help of for loop.
1. for ( i=0; i<n; i++)
if(i % 2 == 0)
sum_even+=i;
2. for( i=0; i<n; i+=2)
sum_even+=i;

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Software Power Optimizations
 A prerequisite to optimizing a program for low power
must always be to design an algorithm that maps well to
available hardware and is efficient for the problem at hand
in terms of both time and storage complexity.
 Algorithm Computations to match Computational
Resources
 In parallel processor applications, a typical problem is to
structure software in a way that maximizes the available
parallelism.

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Algorithm Computations to match Computational Resources

Parallel computing resources can then be used to speed up


program execution.
 In low-power DSP synthesis, a typical problem is to
design an algorithm to allow a circuit implementation that
minimizes power dissipation given throughput and area
constraints. Often a low-power DSP design will also
exploit parallelism in an algorithm, but the objective is to
shorten critical paths so that supply voltages can be
lowered while maintaining overall performance.

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 If only one adder is available, then Figure 8.1 is a sensible approach. Parallelizing the summation would only force us to use additional registers to store intermediate
sums.

Algorithm Computations to match Computational Resources

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One
Adder

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Algorithm Computations to match Computational Resources

 If two adders are available, then the algorithm illustrated


in Figure 8.2 makes sense because it permits two additions
to be performed simultaneously.

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Two Adders

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Algorithm Computations to match Computational Resources

In the general case, one cannot manipulate the parallelism


of an algorithm quite so conveniently.
 However, the principle is still applicable. The basic
principle is to try to match the degree of parallelism in an
algorithm to the number of parallel resources available.

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Minimizing Memory Access Costs

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Minimizing Memory Access Costs

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Minimizing Memory Access Costs

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Minimizing Memory Access Costs

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Instruction Selection and Ordering
Similar to gate input reordering

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Reference
1. Low-Power CMOS VLSI Circuit Design,
Kaushik Roy and Sharat C Prasad, Wiley Student Edition,
2009
2. http://uploading.com/files/get/39f8aa41/

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THANK
YOU

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