Chapter # 4: Programmable and Steering Logic

Contemporary Logic Design
Prog. & Steering Logic
Chapter # 4: Programmable
and
Steering Logic
Randy H. Katz
University of California, Berkeley
June 1993
© R.H. Katz Transparency No. 4-1

Chapter Overview Prog. & Steering Logic
• PALs and PLAs
• Non-Gate Logic
Switch Logic
Multiplexers/Selecters and Decoders
Tri-State Gates/Open Collector Gates
ROM
• Combinational Logic Design Problems

Seven Segment Display Decoder
Process Line Controller
Logical Function Unit
Barrel Shifter

PALs and Prog. & Steering Logic
PLAs
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form
Inputs
Dense array of Dense array of

AND gates Product OR gates
terms
Outputs

PLAs
Key to Success: Shared Product Terms
Equations
F0 = A + B' C'
Example: F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:
Personality Matrix 1 = asserted in term
0 = negated in term
Product Inputs Outputs - = does not participate
term A B C F0 F1 F2 F3
AB 1 1 - 0 1 1 0 Output Side:
BC - 0 1 0 0 0 1 Reuse 1 = term connected to output
of 0 = no connection to output
AC 1 - 0 0 1 0 0
terms
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1

PLAs
Example Continued
All possible connections are available

before programming

PLAs
Example Continued
Unwanted connections are "blown"
Note: some array structures

work by making connections
rather than breaking them

PLAs
Alternative representation for high fan-in structures
Short-hand notation
so we don't have to
draw all the wires!
Notation for implementing

F0 = A B + A' B'
F1 = C D' + C' D

PLAs
Design Example
Multiple functions of A, B, C ABC
A
F1 = A B C
B
F2 = A + B + C C
A
F3 = A B C
B
F4 = A + B + C C
F5 = A xor B xor C ABC
ABC
F6 = A xnor B xnor C
ABC
ABC
ABC
ABC
ABC
F1 F2 F3 F4 F5 F6

PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept — implemented by Monolithic Memories

constrained topology of the OR Array
A given column of the OR array

has access to only a subset of
the possible product terms
PLA concept — generalized topologies in AND and OR planes

PLAs
Design Example: BCD to Gray Code Converter
Truth Table K-maps
A B C D W X Y Z A A
0 0 0 0 0 0 0 0 AB AB
0 0 0 1 0 0 0 1 CD 00 01 11 10 CD 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0 01 0 1 X 1 01 0 1 X 0
0 1 1 0 1 0 1 0 D D
0 1 1 1 1 0 1 1 11 0 1 X X 11 0 0 X X
1 0 0 0 1 0 0 1 C C
1 0 0 1 1 0 0 0 10 0 1 X X 10 0 0 X X
1 0 1 0 X X X X
1 0 1 1 X X X X B B
1 1 0 0 X X X X
K-map for W K-map for X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X A A
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 1 X 0 00 0 0 X 1
01 0 1 X 0 01 1 0 X 0
Minimized Functions: D D
11 1 1 X X 11 0 1 X X
W=A+BD+BC 10
C
1 1 X X
C
10 1 0 X X
X = B C'
Y=B+C B B
Z = A'B'C'D + B C D + A D' + B' C D' K-map for Y K-map for Z

PLAs
Programmed PAL:
ABCD
4 product terms per each OR gate

PLAs
Code Converter Discrete Gate Implementation
\A \A
A 1
\B
4
\C
B D
2 3 W
D
B
C 3
B 2 D
C 4 4 Z
A
5
B D 1 \D
22 1 X \B
C 1
C 3
\C \D
1: 7404 hex inverters

2 Y
B 1 2,5: 7400 quad 2-input NAND
\B 3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND
4 SSI Packages vs. 1 PLA/PAL Package!

PLAs
Another Example: Magnitude Comparator
A A
AB AB
00 01 11 10 00 01 11 10
ABCD
CD CD
00 1 0 0 0 00 0 1 1 1 ABCD
01 0 1 0 0 01 1 0 1 1 ABCD
D D
11 0 0 1 0 11 1 1 0 1 ABCD
C C
10 0 0 0 1 10 1 1 1 0 AC
B B AC
K-map for EQ K-map for NE
BD
A A BD
AB AB
CD 00 01 11 10 CD 00 01 11 10
ABD
00 0 0 0 0 00 0 1 1 1
BCD
01 1 0 0 0 01 0 0 1 1
D D ABC
11 1 1 0 1 11 0 0 0 0
C C BCD
10 1 1 0 0 10 0 0 1 0
B B
K-map for LT K-map for GT
EQ NE LT GT

Non-Gate Prog. & Steering Logic
Logic
Introduction
AND-OR-Invert Generalized Building Blocks
PAL/PLA Beyond Simple Gates
Kinds of "Non-gate logic":
• switching circuits built from CMOS transmission gates
• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories

Steering Logic: Prog. & Steering Logic
Switches
Voltage Controlled Switches
Channel
Region
Gate
Oxide
Source Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is

formed

Steering Prog. & Steering Logic
Logic
Voltage Controlled Switches
Gate
Logic 1 on gate,
Source Drain Source and Drain connected
nMOS Transistor
Gate
Logic 0 on gate,
Source and Drain connected
Source Drain
pMOS Transistor

Logic
Logic Gates from Switches
+5V A B A B
+5V +5V
A AB
A
A+B
Inverter NAND Gate NOR Gate
Pull-up network constructed from pMOS transistors
Pull-down network constructed from nMOS transistors

Logic
Inverter Operation
+5V +5V
"1" "0" "0" "1"
Input is 1 Input is 0
Pull-up does not conduct Pull-up conducts
Pull-down conducts Pull-down does not conduct
Output connected to GND Output connected to VDD

Logic
NAND Gate Operation
"1" "1" "0" "1"
+5V +5V
"0" "1"
A = 1, B = 1 A = 0, B = 1
Pull-up network does not conduct Pull-up network has path to VDD
Pull-down network conducts Pull-down network path broken
Output node connected to GND Output node connected to VDD

Logic
NOR Gate Operation
"0" "0" "1" "0"

+5V +5V
"1" "0"
A = 0, B = 0 A = 1, B = 0
Pull-up network conducts Pull-up network broken
Pull-down network broken Pull-down network conducts
Output node at VDD Output node at GND

Logic
CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's
pMOS transistors good at passing 1's but bad at passing 0's
perfect "transmission" gate places these in parallel:
Control Control Control
In Out
In Out In Out
Control Control
Control
Switches Transistors Transmission or

"Butterfly" Gate

Logic
Selection Function/Demultiplexer Function with Transmission Gates
S
Selector: I
Choose I0 if S = 0 0
Choose I1 if S = 1 S
S Z
I
1
S
Z0
Demultiplexer:
I to Z0 if S = 0 S
I S
I to Z1 if S = 1
Z1
S

Logic
Use of Multiplexer/Demultiplexer in Digital Systems
A Y
Demultiplexers Multiplexers
B Z
A Y
Demultiplexers Multiplexers
B Z
So far, we've only seen point-to-point connections among gates
Mux/Demux used to implement multiple source/multiple destination

interconnect
Logic
Well-formed Switching Networks
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
Z0
"0"
I
S S
Z1
"0"
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"

Logic
Complex Steering Logic Example
N Input Tally Circuit: count # of 1's in the inputs
I1
I Zero One
1 Straight Through
I1
0 1 0 "0" One
1 0 1 "0" One
"1" Zero
I1 Zero Diagonal
"0"
One "1" Zero
Conventional Logic
for 1 Input Tally
Function "0"
Switch Logic Implementation

of Tally Function

Logic
Operation of the 1 Input Tally Circuit
"0"
"0" One "0"
"0" One
"1" Zero
"0"
"1" Zero
"0"
Input is 0, straight through switches enabled

Logic
Operation of 1 input Tally Circuit
"1"
"0" One
"1"
"0" One
"1" Zero
"1" "0"
Zero
"0"
Input = 1, diagonal switches enabled

Logic
Extension to the 2-input case
I 1 I2 Zero One Two I1

Zero
0 0 1 0 0 I2
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1 One
Two
Conventional logic implementation

Logic
Switch Logic Implementation: 2-input Tally Circuit
I2 I2
I1
"0" Two
"0" Two One

"0" One
Zero
"1" Zero
"0" "0"
I1
One
"0" One
Cascade the 1-input implementation!

Zero
"1" Zero
"0" "0"

Logic
Operation of 2-input implementation
"0"
"0"
"0" "1"
"0" "0" "0" "0"
One One
"0" "0" "0" "1"
Zero Zero
"1" "1" "0"
"1"
"0" "0" "0" "0"
"1"
"1"
"0" "1"
"0" "0" "0" "1"
One One
"0" "1" "0" "0"
Zero Zero
"1" "0" "1" "0"
"0" "0" "0" "0"

Multiplexers/Selectors Prog. & Steering Logic
Use of Multiplexers/Selectors
Multi-point connections
A0 A1 B0 B1
Multiple input sources
Sa MUX MUX Sb
A B
Sum
Ss DEMUX Multiple output destinations
S0 S1

General Concept
n
2 data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
Z = A' I 0 + A I 1
A Z I1 I0 A Z
0 I0 0 0 0 0
1 I1 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
Functional form 1 0 1 1
Logical form 1 1 0 1
1 1 1 1
Two alternative forms

for a 2:1 Mux Truth Table
I0
2:1
mux Z Z = A' I 0 + A I 1
I1
I0
I1
4:1
I2 mux
Z Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
I3
A B
I0
I1
I2
I3
I4
8:1
Z Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
mux
I5 A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
I6
I7 n
In general, Z =  2 -1m I
k=0 k k
A B C in minterm shorthand form for a 2 n :1 Mux

Alternative Implementations
A B
I0 Z
I1
I2
I3
Gate
GateLevel
Level Transmission
TransmissionGate
Gate
Implementation
Implementation Implementation
Implementationof
of
of
of4:1
4:1Mux
Mux 4:1
4:1Mux
Mux
thirty six transistors twenty transistors

Multiplexer/Selector Prog. & Steering Logic
Large multiplexers can be implemented by cascaded smaller ones
I0 Control signals B and C simultaneously

0 4:1 8:1
I1 1 mux mux choose one of I0-I3 and I4-I7
I2 2
I3 3S S
1 0 0 2:1 Z Control signal A chooses which of the
mux upper or lower MUX's output to gate to Z
I4 0 4:1 1 S
I5 1 mux
I0 0
I6 2 I1 1 S
I7 3 S1 S0
C
I2 0
B C A 0
I3 1 S
1
Alternative 8:1 Mux Implementation C 2
Z
I4 0
3 S0 S1
I5 1 S
A B
C
I6 0
I7 1 S
C
Multiplexers/selectors as a general purpose logic block

n-1
2 :1 multiplexer can implement any function of n variables
n-1 control variables; remaining variable is a data input to the mux

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1 0 A B C F
0 1 0 0 0 1 C 0
1 C F
2 F 0 0 1 0 C 1 4:1
0 3 8:1 0
0 1 0 1 2 MUX
0 4 MUX C 1
0 0 1 1 0 3
5 S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1 1
A B C
1 1 1 1
"Lookup Table"

Generalization
I 1 I 2 … In F
0 0 0 1 1 Four possible
… configurations
n-1 Mux 0 1 0 1
control variables 1 of the truth table rows
single Mux
data variable 0 In In 1 Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
1 0
K-map D 1
Choose A,B,C 0 2
as control variables 8:1 G
1 3
D 4 mux
D 5
Multiplexer D 6
Implementation D 7 S2 S1 S0
TTL
TTLpackage
packageefficient
efficient A B C
May be gate inefficient
May be gate inefficient
Decoders/Demultiplexers Prog. & Steering Logic
Decoder: single data input, n control inputs, 2 n outputs
control inputs (called select S) represent Binary index of output to which

the input is connected
data input usually called "enable" (G)
1:2 Decoder: 3:8 Decoder:

O0 = G • S; O1 = G • S O0 = G • S0 • S1 • S2
O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1 O2 = G • S0 • S1 • S2
O1 = G • S0 • S1 O3 = G • S0 • S1 • S2
O2 = G • S0 • S1 O4 = G • S0 • S1 • S2
O3 = G • S0 • S1 O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
O7 = G • S0 • S1 • S2

Alternative Implementations
G /G
Output0 Select Output0
Select
Output1 Output1
1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable
G /G
Output0 Output0
Output1 Output1
Output2 Output2
Output3 Output3
Select0 Select1 Select0 Select1
2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable

Switch Logic Implementations
Select
Select G Output
0
G Output Select
0 Select
Select "0"
Select
Select
Output Select
1
Select Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times "0"
Select
Correct 1:2 Decoder Implementation

Switch Implementation of 2:4 Decoder
Select Select
0 1
G Output
0
"0" Operation of 2:4 Decoder

"0"
S0 = 0, S1 = 0
G Output
1
one straight thru path
"0"
three diagonal paths
"0"
G Output
2
"0"
"0"
G Output
3
"0"
"0"

Decoder/Demultiplexer Prog. & Steering Logic
Decoder as a Logic Building Block
0 ABC
1 ABC
2 ABC Decoder Generates Appropriate
Enb
3:8 3 ABC Minterm based on Control Signals
dec 4 ABC
5 ABC
6 ABC
S2 S1 S0 7 ABC
A B C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

Decoder/Demultiplexer Prog. & Steering Logic
Decoder as a Logic Building Block

0 A BC D
1 ABC D
F1
2 ABC D
3 ABC D
4 ABC D
5 ABC D
Enb 6 ABC D
4:16
7 ABC D
dec
8 ABC D F2
9 ABC D
10 ABC D
11 ABC D
12 ABC D
13 ABC D
14 ABC D
F3
S3 S2 S1 S0 15 ABC D
A B C D
If active low enable, then use NAND gates!

Multiplexers/Decoders Prog. & Steering Logic
Alternative Implementations of 32:1 Mux
EN 1 1G 1Y3 7 7 EN 146
I31 7 151 6 5
1391Y2 I31 7 151 154
EN 1 6 A 3 1B 1Y1 5
6 1 3
5 2 1A 1Y0 4 7 EN
I23 7 151 1 Y5 B I5 145 22
41 4 15 2G 2Y3 9 I23 7 I4151 154 31 Y 5
6 3 W 6 2Y2 10 40
EN 1 5 52 2 13 2B 2Y1 11 7 EN 146 I3 1 2
3 W 6
I15 7 151 1 3 1 5 I5 5 I2 2 9C
1 41 4 40Y 6 14 2A 2Y0 12 I15 7 I4151154 I1 3 1 Y 105B
EN 1 6 52 3 3 I0 4 0 W 116A
5 2 W 1 GA 7 EN 146 I3 1
I7 7 151
3
1 3 1 Y 19
5C 153 I5 5 I2 22 C 9 C S2 F(A, B, C, D, E)
41 4 4 0W 1 6AB 3 A3 154 I1 31Y 10
I7 7 I4151 5B
I6 6 5 3 0 4 A2 I6 6 I3 1 3 I0 40WD 116A S1
I5 5 22 9 5 A1 YA 7 F(A, B, C, D, E)
I4 4 3 1 Y 15 C 1 I5 5 I2 2 2 C 9C S2E S0
4 0 1 6B 6 A0 I4 4 I1 3 1 Y 105
I3 13 D 11BS1
I2 2 9
W0 A
13 B3 I3 3 I0 4 0 W 6A
I1 1 1 C B
1 12 B2 I2 2 C 9 S2
I1 1 10C
E S0
I0 0 1A 11 B1 YB 9 D B
S1
C S2 0 10 I0 0 11A
1 B0
D C S2E S0
S1 1 GBS1 SO
E D S1
S0 5 2 14 E S0
A B
Multiplexer Only Multiplexer + Decoder

Multiplexers/Decoders Prog. & Steering Logic
5:32 Decoder
G1 Y7 \Y31
\EN 1G 1Y3 G2A Y6 \Y30
139 1Y2 G2B Y5 \Y29
S4
S3 1B 1Y1 Y4 \Y28
138 Y3
1A 1Y0 \Y27
S2 C Y2 \Y26
2G 2Y3 S1 Y1 \Y25
2Y2 B
S0 Y0 \Y24
2B 2Y1 A
2A 2Y0
G1 Y7 \Y23
\EN \Y31 G2A Y6 \Y22
G2B Y5 \Y21
\Y20
138 Y4 \Y19
5:32 . S2
Y3
Y2 \Y18
Decoder . S1 C
Y1 \Y17
B
Subsystem . S0
A Y0 \Y16
\Y15
\Y0 G1 Y7
\Y14
G2A Y6
\Y13
S4 S3 S2 S1 S0 G2B Y5
\Y12
138 Y4 \Y11
Y3
S2 \Y10
C Y2
S1 B Y1 \Y9
S0 A Y0 \Y8
\Y7
G1 Y7
\Y6
G2A Y6 \Y5
G2B Y5
\Y4
138 Y4 \Y3
Y3
S2 \Y2
C Y2
S1 Y1 \Y1
B
S0 Y0 \Y0
A

Tri-State and Open- Prog. & Steering Logic
Collector
The Third State
Logic States: "0", "1"
Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" — high impedance — infinite resistance, no connection
Tri-state gates: output values are "0", "1", and "Z"

additional input: output enable (OE)
When OE is high, this gate is a non-inverting "buffer"
A OE F
X 0 Z When OE is low, it is as though the gate was
0 1 0 disconnected from the output!
1 1 1 This allows more than one gate to be connected to the
same output wire, as long as only one has its
output enabled at the same time
100
A
Non-inverting buffer's
timing waveform OE
F
"Z" "Z"
Tri-state and Open Prog. & Steering Logic
Collector
Using tri-state gates to implement an economical multiplexer:
Input 0 F
OE
When SelectInput is asserted high
Input Input1 is connected to F
1
When SelectInput is driven low

OE Input0 is connected to F
This is essentially a 2:1 Mux
SelectInput

Tri-state and Open Prog. & Steering Logic
Collector
Alternative Tri-state Fragment
Input 0
F
Active low tri-state enables
plus inverting tri-state buffers
OE
Input 1
1
OE
SelectInput
F
I
OE
Switch Level Implementation

of tri-state gate 0

Tri-State and Open Prog. & Steering Logic
Collector
4:1 Multiplexer, Revisited
\EN 1 1G 1Y3
7
1Y2 6
3 139 5
S1 1B 1Y1 D3
2 1A 1Y0 4
S0
15 9
2G 2Y3 10
2Y2 D2
13 2B
2Y1 11
14 2A
2Y0 12
D1
D0
Decoder + 4 tri-state Gates

Collector
Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot actively
drive the wire high
this is done by pulling the wire up to a logic 1 voltage through a

resistor
+5 V
Pull-up resistor
OC NAND gates
Open-collector
NAND gate
Wired AND:
If A and B are "1", output is actively pulled low
F if C and D are "1", output is actively pulled low
0V
if one gate is low, the other high, then low wins
A B if both gates are "1", the output floats, pulled
high by resistor
Hence, the two NAND functions are AND'd
together!

Collector
4:1 Multiplexer
+5V
\EN 1 G Y3 7
139 Y2 6
S1 3 B Y1 5
S0 2 A Y0 4
\I3 OR F
\I2 OR
\I1 OR
\I0 OR
Decoder + 4 Open Collector Gates

Read-Only Memories Prog. & Steering Logic
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V
n
2 -1
i Word Line 0011

Dec
j Word Line 1010
Bit Lines
0 n-1
Address
Internal Organization

Example: Combination Logic Implementation
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'

Address A B C F0 F1 F2 F3 Word Contents
0 0 0 0 0 1 0
0 0 1 1 1 1 0
0 1 0 0 1 0 0
ROM 0 1 1 0 0 0 1
8 w ords ¥by 1 0 0 1 0 1 1
4 bits 1 0 1 1 0 0 0
1 1 0 0 0 0 1
1 1 1 0 1 0 0
A B C F0 F1 F2 F3
address outputs

Not Memory array

Notunlike
unlikeaaPLA
PLA
structure
structure withaa
with
fully
fullydecoded
decoded Decoder
2n word 2n words by
AND
ANDarray!
array! lines m bits
n address m output
lines lines
ROM vs. PLA:

ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when

(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes

2764 EPROM 2764 2764

8K x 8 +
VPP
PGM +
VPP
PGM
A12 A12
A11 A11
2764 A10 O7 A10 O7
A9 O6 A9 O6
VPP A8 O5 A8 O5
A7 O4 A7 O4
PGM A6 O3 A6 O3
A12 A5 O2 A5 O2
A4 O1 A4 O1
A11 A3 O0 A3 O0
A2 A2
A10 O7 A1 A1
A0 A0
A9 O6 CS U3 CS U2
A8 OE OE
O5
A7 O4
A13
A6 /OE
O3 A12:A0
A5 O2 D15:D8
A4 D7:D0
O1 2764 2764
A3 O0 + VPP
+
VPP
PGM PGM
A2 A12 A12
A11 A11
A1 A10 O7 A10 O7
A9 O6 A9 O6
A0 A8 O5 A8 O5
CS A7 O4 A7 O4
A6 O3 A6 O3
OE A5 O2 A5 O2
A4 O1 A4 O1
A3 O0 A3 O0
A2 A2
A1 A1
A0 A0
CS U1 CS U0
OE OE
16K x 16
Subsystem
Combinational Logic Word Prog. & Steering Logic
Problems
General Design Procedure
1. Understand the Problem
what is the circuit supposed to do?
write down inputs (data, control) and outputs
draw block diagram or other picture
2. Formulate the Problem in terms of a truth table or other suitable

design representation
truth table or waveform diagram
3. Choose Implementation Target

ROM, PAL, PLA, Mux, Decoder + OR, Discrete Gates
4. Follow Implementation Procedure

K-maps, espresso, misII

Problems
Process Line Control Problem
Statement of the Problem

Rods of varying length (+/-10%) travel on conveyor belt
Mechanical arm pushes rods within spec (+/-5%) to one side
Second arm pushes rods too long to other side
Rods too short stay on belt
3 light barriers (light source + photocell) as sensors
Design combinational logic to activate the arms
Understanding the Problem

Inputs are three sensors, outputs are two arm control signals
Assume sensor reads "1" when tripped, "0" otherwise
Call sensors A, B, C
Draw a picture!

Problems
Process Control Problem
+10%
+ 5% + 5%
Spec Spec Spec
- 5% - 5%
- 10%
ROD ROD ROD
Too Within Too
Long Spec Short
Where to place the light sensors A, B, and C to distinguish among

the three cases?
Assume that A detects the leading edge of the rod on the conveyor

Problems
Spectification
- 5%
Too Within Too Specification
Long Spec Short + 5%
A to B distance place apart at specification - 5%
A to C distance placed apart at specification +5%

Problems
A B C Function
0 0 0 X
0 0 1 X Truth table and logic implementation
0 1 0 X now straightforward
0 1 1 X
1 0 0 too short "too long" = A B C
1 0 1 X (all three sensors tripped)
1 1 0 in spec
"in spec" = A B C'
1 1 1 too long (first two sensors tripped)

Problems
BCD to 7 Segment Display Controller
Understanding the problem:
input is a 4 bit bcd digit
output is the control signals for the display
4 inputs A, B, C, D
7-Segment
7 outputs C0 — C6 display
C0 C0 C1 C2 C3 C4 C5 C6
C5 C1
C6
C4 C2 BCD-to-7-segment
C3 control signal
decoder
C C C C C C C
0 1 2 3 4 5 6
A B C D
Block Diagram
Problems
Formulate the problem in terms of a

truth table
Choose implementation target:

if ROM, we are done
don't cares imply PAL/PLA may be

attractive
Follow implementation procedure:

hand reduced K-maps
vs.
espresso

Problems
A A A
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 1 0 X 1 00 1 1 X 1 00 1 1 X 1
01 0 1 X 1 01 1 0 X 1 01 1 1 X 1
D D D
11 1 1 X X 11 1 1 X X 11 1 1 X X
C C C
10 1 1 X X 10 1 0 X X 10 0 1 X X
B B B
K-map for C0 K-map for C1 K-map for C2
A A A A
AB AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 1 0 X 1 00 1 0 X 1 00 1 1 X 1 00 0 1 X 1
01 0 1 X 0 01 0 0 X 0 01 0 1 X 1 01 0 1 X 1
D D D D
11 1 0 X X 11 0 0 X X 11 0 0 X X 11 1 0 X X
C C C C
10 1 1 X X 10 1 1 X X 10 0 1 X X 10 1 1 X X
B B B B
K-map for C3 K-map for C4 K-map for C5 K-map for C6
C0 = A + B D + C + B' D' C3 = B' D' + C D' + B C' D + B' C

C1 = A + C' D' + C D + B' C4 = B' D' + C D
C2 = A + B + C' + D C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C
14 Unique Product Terms
Problems
BCD to 7 Segment 1
Increment
0 4 8 12 16 20 24 28
Display ControllerFirst
fuse
numbers
0
32
64
96
128 19
160
192
224
2
256
288
320
352 18
384
416
448
480
3
512
16H8PAL 544
576
608
640 17
Can Implement 672

704
736
the function
4
768
800
832
864 16
896
928
960
992
5
1024
1056
1088
1120 15
1152
1184
1216
1248
6
1280
1312
1344
1376 14
1408
1440
1472
1504
7
1536
1568
1600
1632
1664 13
1696
1728
1760
8
1792
1824
1856
1888 12
1920
1952
1984
2016
9 11
Note: Fuse number = first fuse number + increment

Problems
BCD to 7 Segment
Display Controller Increment
012 3 4 8 10 12 14 16 18 20 24 27
2 23
First 0
fuse 28 22
1
numbers 56
84
14H8PAL 3
112
Cannot Implement
21
140
the function 168

196
20
224 19
252
280 18
308
336 17
364
392 16
420
448
476 15
504
532
10 14
11 13
Note: Fuse number = first fuse number + increment

Problems
BCD to7 Segment Display Controller
.i 4 .i 4
.o 7 .o 7
.ilb a b c d .ilb a b c d
.ob c0 c1 c2 c3 c4 c5 c6 .ob c0 c1 c2 c3 c4 c5 c6
.p 16 .p 9
0000 1111110 -10- 0000001
0001 0110000 -01- 0001001
0010 1101101 -0-1 0110000 C0 = B C' D + C D + B' D' + B C D' + A
0011 1111001 -101 1011010 C1 = B' D + C' D' + C D + B' D'
0100 0110011 --00 0110010 C2 = B' D + B C' D + C' D' + C D + B C D'
0101 1011011 --11 1110000
-0-0 1101100 C3 = B C' D + B' D + B' D' + B C D'
0110 1011111
0111 1110000 1--- 1000011 C4 = B' D' + B C D'
1000 1111111 -110 1011111 C5 = B C' D + C' D' + A + B C D'
1001 1110011 .e C6 = B' C + B C' + B C D' + A
1010 -------
1011 ------- espresso 9 Unique Product Terms!
1100 ------- output
1101 -------
1110 -------
1111 -------
.e 63 Literals, 20 Gates
espresso
input

Problems
PLA Implementation

Problems
BCD to7 Segment Display Controller
Multilevel Implementation
X = C' + D'
Y = B' C'
C0 = C3 + A' B X' + A D Y
52 literals
C1 = Y + A' C5' + C' D' C6
33 gates
C2 = C5 + A' B' D + A' C D
Ineffective use of don't cares
C3 = C4 + B D C5 + A' B' X'
C4 = D' Y + A' C D'
C5 = C' C4 + A Y + A' B X
C6 = A C4 + C C5 + C4' C5 + A' B' C

Problems
Statement of the Problem:
3 control inputs: C0, C1, C2

2 data inputs: A, B
1 output: F

Problems
Formulate as a truth table
Choose implementation technology

5-variable K-map
espresso
multiplexor implementation
A
B 4 TTL packages:
A
4 x 2-input NAND
B
4 x 2-input NOR
2 x 2-input XOR
A 8:1 MUX
B
+
5
V
DD D D D D D D S C2
01 2 3 4 5 6 7 0
S C1
E
N 1
Q S C0
O 2
F

Problems
Follow implementation procedure

C1 C2
AB 00 01 11 10
C0=0 00 1 1 F = C2' A' B' + C0' A B'
+ C0' A' B + C1' A B
01 1 1 1 1
11 1 1 5 gates, 5 inverters
10 1 1 1 1 Also four packages:
4 x 3-input NAND
C1 C2 1 x 4-input NAND
AB 00 01 11 10
C0=1 00 1 1
Alternative: 32 x 1-bit ROM
01
single package
11 1 1
10

Problems
8-Input Barrel Shifter
Specification:
Inputs: D7, D6, …, D0 shift input the specified number
Outputs: O7, O6, …, O0
of positions to the right
Control: S2, S1, S0
Understand the problem:
D7 O7 D7 O7 D7 O7
D6 O6 D6 O6 D6 O6
D5 . O5 D5 . O5 D5 . O5
D4 . O4 D4 . O4 D4 . O4
D3 . O3 D3 . O3 D3 . O3
D2 O2 D2 O2 D2 O2
D1 O1 D1 O1 D1 O1
D0 O0 D0 O0 D0 O0
S2, S1, S0 = 0 0 0 S2, S1, S0 = 0 0 1
S2, S1, S0 = 0 1 0

Problems
S2 S1 S0 O7 O6 O5 O4 O3 O2 O1 O0
Function Table 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 D6 D5 D4 D3 D2 D1 D0 D7
0 1 0 D5 D4 D3 D2 D1 D0 D7 D6
0 1 1 D4 D3 D2 D1 D0 D7 D6 D5
1 0 0 D3 D2 D1 D0 D7 D6 D5 D4
1 0 1 D2 D1 D0 D7 D6 D5 D4 D3
1 1 0 D1 D0 D7 D6 D5 D4 D3 D2
1 1 1 D0 D7 D6 D5 D4 D3 D2 D1
Boolean O7 = S2' S1' S0' D7 + S2' S1' S0 D6 + … + S2 S1 S0 D0

equations
O6 = S2' S1' S0' D6 + S2' S1' S0 D5 + … + S2 S1 S0 D7
O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + … + S2 S1 S0 D6
O4 = S2' S1' S0' D4 + S2' S1' S0 D3 + … + S2 S1 S0 D5
O3 = S2' S1' S0' D3 + S2' S1' S0 D2 + … + S2 S1 S0 D4
O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + … + S2 S1 S0 D3
O1 = S2' S1' S0' D1 + S2' S1' S0 D0 + … + S2 S1 S0 D2
O0 = S2' S1' S0' D0 + S2' S1' S0 D7 + … + S2 S1 S0 D1

Problems
Straightforward gate logic implementation OR
8 by 8:1 multiplexer (wiring mess!) OR
Switch logic
O7 O6 O5 O4 O3 O2 O1 O0 O7 O6 O5 O4 O3 O2 O1 O0
S000 S000
D7 D7
S001 S001 S001
S001 D6
D6
S010 S010
D5 D5
S011
S011
D4 D4
S100
S100
D3 D3
S101
S101
D2 D2
S110
S110
D1 D1
S111
S111
D0 D0
Crosspoint switches Fully Wired crosspoint switch

Chapter Review Prog. & Steering Logic
• Non-Simple Gate Logic Building Blocks:

PALs/PLAs
Multiplexers/Selecters
Decoders
ROMs
Tri-state, Open Collector
• Combinational Word Problems:

Understand the Problem
Formulate in terms of a Truth Table
Choose implementation technology
Implement by following the design procedure

Chapter # 4: Programmable and Steering Logic

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Contemporary Logic Design

Prog. & Steering Logic

Contemporary Logic Design

© R.H. Katz Transparency No. 4-1

• PALs and PLAs

• Combinational Logic Design Problems

© R.H. Katz Transparency No. 4-2

Programmable Array Block Diagram for Sum of Products Form

Dense array of Dense array of

© R.H. Katz Transparency No. 4-3

© R.H. Katz Transparency No. 4-4

All possible connections are available

© R.H. Katz Transparency No. 4-5

Unwanted connections are "blown"

Note: some array structures

© R.H. Katz Transparency No. 4-6

Notation for implementing

© R.H. Katz Transparency No. 4-7

Multiple functions of A, B, C ABC

F5 = A xor B xor C ABC

© R.H. Katz Transparency No. 4-8

PAL concept — implemented by Monolithic Memories

A given column of the OR array

PLA concept — generalized topologies in AND and OR planes

© R.H. Katz Transparency No. 4-9

© R.H. Katz Transparency No. 4-10

4 product terms per each OR gate

© R.H. Katz Transparency No. 4-11

1: 7404 hex inverters

4 SSI Packages vs. 1 PLA/PAL Package!

© R.H. Katz Transparency No. 4-12

© R.H. Katz Transparency No. 4-13

Kinds of "Non-gate logic":

• switching circuits built from CMOS transmission gates

• tri-state and open collector gates

© R.H. Katz Transparency No. 4-14

Diffusion regions: negatively charged ions driven into Si surface

Si Bulk: positively charged ions

By "pulling" electrons to the surface, a conducting channel is

© R.H. Katz Transparency No. 4-15

© R.H. Katz Transparency No. 4-16

Inverter NAND Gate NOR Gate

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors

© R.H. Katz Transparency No. 4-17

"1" "0" "0" "1"

© R.H. Katz Transparency No. 4-18

© R.H. Katz Transparency No. 4-19

"0" "0" "1" "0"

© R.H. Katz Transparency No. 4-20

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

Control Control Control

Switches Transistors Transmission or

© R.H. Katz Transparency No. 4-21

© R.H. Katz Transparency No. 4-22

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

© R.H. Katz Transparency No. 4-24

One "1" Zero