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Vdd
s-a-on
• The s-a-0/1 fault model accounts for most physical fault types but not all. E.g., it does not account for ‘bridging’ faults) since we cannot say if
either wire is s-a-0 or s-a-1—this situation will change dynamically based on the values (1 or 0) being driven on the wires and which driver is
stronger
s-a-1
Wire break (s-a-0) Wire short to GND (s-a-0) Defective transistor (always on)
vector 0 1 1 0 1
Compare 1 0 0 0 0
1 0 1 0 1
Expected
responses 1 1 0 1 1
1 1 1 1 1
• Need to determine a minimum set of inputs that can test for
(detect/catch) any single fault. Single fault detection is a good goal as:
• Probability of multiple faults is much lower than single faults
• Mutiple faults take much more time to detect
Test Generation
• Function: f(x1,…,xn) (≡f(Xn)) represents the fault-free
circuit.
• A test Ti for fault p/d is an input vector Xnj to the circuit
for which:
fp/d(Xnj) = f(Xnj)
where j is the decimal value of the n bit binary input.
• E.g., X31 =001 is a test for 3/0 for the earlier example:
[f(x3)=x1x2+x3, f3/0(x )=x1x2] as f(X31)=1 and f3/0(x31)=0
3
Tests Faults
x1 x2 x3 1/0 1/1 2/0 2/1 3/0 3/1 4/0 4/1 5/0 5/1
0 0 0 0 0 0 0 0 1 0 1 0 1
0 0 1 0 0 0 0 1 0 0 0 1 0
0 1 0 0 1 0 0 0 1 0 1 0 1
0 1 1 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 0 1 0 1 0 1 0 1
1 0 1 0 0 0 0 1 0 0 0 1 0
1 1 0 1 0 1 0 0 0 1 0 1 0
1 1 1 0 0 0 0 0 0 0 0 1 0
Determining a Minimal Test Set
• A test set for a fault set S is a set of i/p vectors (also called test vectors [TVs]) which contains at least
one test for each fault in S
• From the fault table, we need to determine a minimal test set that covers all faults in the table (the set of
faults in the table is the set S)
• Determining a minimal test set lower testing cost in terms of
– Test time (this allows, for ex, product to get to market faster after manufacturing testing)
– Power consumption during testing
• Determining a minimal test set is a minimal covering problem, just like in the PIT part of QM where we
need to cover all MTs w/ a minimal set of PIs (this is especially true in PLA design, where each PI has a
cost of 1).
– Here, TVs PIs and faults MTs
– So a QM-type method can be used for covering all faults using a minimal set of TVs
– TV cost = 1, and since there is no multi-function type issue as in QM for logic min., costs are not mentioned
OR gate w/ s-a-0 OR gate w/ s-a-1 AND gate w/ s-a-0 AND gate w/ s-a-1
Four input
2/0 2/1 2/0 2/1
x1=0 x1=0 x1=0 x1=0
x2=1 z x2=0 x2=1 z x2=0 z
x3=0 z x3=0 z z x3=0 z x3=0
x4=0 x4=0 x4=0 x4=0 z
2/0 2/1
2/1 2/0
x1=1 x1=1
x2=1 x1=1 x1=1
z x2=0 x2=1 z x2=0 z
x3=1 z z z x3=1 z
x4=1 x3=1 z x3=1
x4=1 x4=1 x4=1
Path Sensitizing method (contd)
Backward trace
BT 1/0 Forward trace
4
1 z 1
x1=1 1 x1=X/0
x2=1 4 f x2=0/X 2 0
f
2 1 z z 3 5 z
x3=0 5 z x3=0 0 z
3 0 3/1
Forward trace
Confirm w/ XOR method:
F1/0=(x1x2+x3) + x3=x1x2x3’ Confirm: F3/1=(x1x2+x3) + 1 =
test for 1/0 = {110} (x1’+x2’)x3’ = x1’ x3’ + x2’x3’
tests for 3/1 = {000, 010, 100}
Path Sensitizing method (contd)
• Facts in fanout-free circuits (circuits in which each gate o/p feeds only 1 gate i/p
or is a ckt o/p) and circuits w/ fanout (at least 1 gate o/p feeds > 1 gate i/ps):
– For a given sensitized path, each wire along the path for p/d is also tested for a s-a-0
or s-a-1 fault as determined as follows:
• For each wire w on the sensitized path, if logic value on w is z, then w is tested for w/d,
otherwise (logic value on w is z’) it is tested for w/d’
• In Fig. 1 below, a test for 3/1 is also a test for 5/1 (the sensitized path is 3 5)
• There is only 1 path from an i/p to an o/p each wire is on at least one (unique) path from
an i/p to an o/p
• Thus fan-out free ckts can be tested for all possible single s-a-0 and s-a-1 faults by testing
each primary input for s-a-0 and s-a-1 faults
• For fanout ckts, if the faulty point has a fanout, then its test will test all sensitized
paths for that test; but all fanout paths from a fault may not be sensitized; so a
faulty point’s test is not necessarily a test for all fanout paths
– Thus should try to do multipath sensitization (either simultaneously or sequentially) if
possible (it is not always!) in fanout ckts. For sensitization of simultaneous paths,
when the paths are reconvergent, then only under special cases (given later) will tests
for the primary fault be tests for wires on these paths
– If after tests for primary i/ps and their sensitized paths are determined for all possible
faults, if some wires remain untested (because a path to them from primary i/ps
cannot be sensitized), start the process from such wire(s) w/ the lowest level and find
tests for them and all their sensitized paths z z’
Backward p1/d p6/d p8/d
trace 1 p7/d’ z
x1=X/0
Test Xnj
Forward trace z z’
d’ z’
4 f z’ p4/d
x2=0/X 2 0 2 sensitized p2/d’
3 z 5 z paths for p1/d p3/d’ z p5/d’
x3=0 0 Fig. 2: Xnj is a test for p1/d, p2/d’, p3/d’, p4/d &
3/1
p5/d’ on path1 and p6/d, p7/d’ & p8/d on path 2
Fig. 1: Test set for 3/1 & 5/1 = {000, 100, 010} if sensitized non-simultaneously
Testing Circuits with Fanout
• Path sensitization: a) Multiple or single paths can be sensitized.
2/0 2/0
1 0 4
x1=1 4 x1=0 0 6
6
z
x2=11 z x2=1 z z
z 1
0 z
x3=0 5 x3=1 5
• Single path sensitized by TV 110; also a test for 4/0, • Another single path sensitized by TV 011; also a
6/0.
test for 5/0 & 6/0.
• Further, the path is sensitized also for fault 2/1, except
for a 0 needed now to be injected on wire 2. Thus if wire • Further, as in the top path sensitization, the
2 is a primary i/p and does not provide any of the “other” vector 001 is a TV for 2/1 (and 5/1, 6/1)
i/ps to any gate on the senstitized path, then just by
changing the corresponding i/p from 1 to 0, we get a test
vector 100 for 2/1 (and 4/1, 6/1). • Double path sensitized by TV 111
Reconvergence • However, this TV is not a test for 4/0, 5/0. E.g., consider fault 4/0.
point/gate of the
Since if 2 is non-faulty (nf)—we are testing for only single faults—
2/0 2 fan-out paths
wire 2 takes on value 1, which causes a 1 on wire 5, thus not
1 4 sensitizing the path from wire 4 to the o/p 6.
x1=1
6 • It is, however, a test for 6/0, since wire 6 occurs after the two paths
z reconverge (check out that 111 injects a 1 into 6)
x2=1 z z
1 z • The corresp. double path sens. based test for 2/1 is 101 (as
x3=1 discussed above)
5
1 • TV 101 is also a test for 4/1, 5/1 and 6/1. E.g., consider 4/1. TV
101 injects a 0 into 4 (needed as the complement of the s-a-1 on 4),
and on 5, needed for sensitizing the path from 4 to o/p 6
Testing Circuits with Fanout---Multipath sensitization
• From the previous example, we can obtain (and prove) the following rules for
determining when a test for an initial fault location p/d determined using multipath
sensitization, is also a test for subsequent wires on these paths:
z z’ p8/d
p1/d p6/d z
p7/d’
o/p1
Test Xnj
z z’
d’ p4/d z’
z’
2 sensitized p2/d’ o/p2
paths for p1/d p3/d’ z p5/d’
• (a) If the multiple sensitized paths are not reconvergent, as shown above, then the wires pj
on each path is also tested by the determined TV(s) for p 1/d, based on whether the logic
variable on wire pj is z—the logic variable on p1—(tested for pj/d) or z’ (tested for pj/d’)
Testing Circuits with Fanout---Multipath sensitization (contd)
z z’ Reconvergence
p1/0 p6 p8 point/gate
p7 or
Test Xnj
z z’ z z z’
1 p4 z
z’
2 sensitized p2 p5 p9/0 p10/1
paths for p1/0 p3 z
z or
z z’ z z’
0 z’ p4/1 z
2 sensitized p2/0 p9/1 p10/0
paths for p1/1 p3/0 z p 5/1
• (c) If: (ii) the test is for p1/1, (ii) the multiple sensitized paths are reconvergent at an OR or NOR gate, and
(iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1/1 are also tests
on subsequent wires pj on these paths for pj/d (d= 1, 0 for logic z, z’ resp. on pj) as shown above
• (d) The above two situations are completely reversed when condition (iii) in (b)-(c) changes to: (iii) the i/ps
to the reconvergent gate are all z’ (the first 2 conditions in (b) remaining unchanged) as follows:
Alternate of (b): All the p1/0 test(s) determined here are also test(s) for the intermediate wires s-a-0/1
(based on z/z’ var, resp. on them) on the sensitized paths. This is b/c for an intermediate wire p j, z’ on the
other path(s) (the one(s) not containing p j) = 0 path through pj via the reconv. OR/NOR gate is
sensitized
Alternate of (c): None of the the p1/1 test(s) determined here are tests on the intermediate wires on these
paths before the reconvergent point (since z’ on the “other” path(s) = 1 thus not sensitizing the path
Testing Circuits with Fanout---Multipath sensitization (contd)
z z’ Reconvergence
p1/1 p6 p7 p8 point/gate
or
Test Xnj
z z’ z z z’
0 z’ p4 z
2 sensitized
p2 p9/1 p10/0
p3 z p5
paths for p1/1
No tests for these wires
• (e) If: (i) the test is for p1/1, (ii) the multiple sensitized paths are reconvergent at an AND or NAND gate,
and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1/1 are not
tests for any pj/d (d= 0 or 1) for wires pj on each path from p1 to the reconverging gate. However, from the
reconvergent point onwards, wires pk are also tested by the determined TV(s) for p 1/1, based on whether the
logic variable on wire pk is z—the logic variable on p1—(tested for pk/1) or z’ (tested for pk/0)
z z’
Reconvergence
p1/0 p6/0 p8/0
j
p7/1 point/gate
n
or
Test X
z z’ z z z’
1 z’ p4/0 z
2 sensitized p2/1 p5/0 p9/0 p10/01
paths for p1/0 p3/1 z
• (f) If: (i) the test is for p1/0, (ii) the multiple sensitized paths are reconvergent at an AND or NAND gate,
and (iii) the i/ps to this gate are all z, as shown above, then the tests determined this way for p 1/0 are also
tests on subsequent wires pj on these paths for pj/d (d= 0, 1 for logic value z, z’, resp., on p j) as shown
above
• (g) The above two situations are completely reversed when condition (iii) in (e)-(f) changes to: (iii) the i/ps
to the reconvergent gate are all z’ (the first 2 conditions remaining unchanged) as follows:
Alternate of (e): All of the p1/1 test(s) determined here are test(s) for the intermediate wires s-a-0/1 (based
on z/z’ var, resp. on them) on the sensitized paths. This is b/c for an intermediate wire p j, z’ on the other
path(s) (the one(s) not containing pj) = 1 path through pj via the recconv. AND/NAND gate is sensitized
Alternate of (f): None of the the p1/0 test(s) determined here are tests on the intermediate wires on these
paths before the reconvergent point (since z’ on the “other” path(s) = 0, thus not sensitzing the path through
pj). They, are, however, tests for wires after the reconvergent gate.
• (h) There cannot be simultaneously sensitized paths reconvergent on 2-i/p XOR/XNOR gates (the paths
Testing Circuits with Fanout (contd)
• Path sensitization (contd)
– b) In some cases, only single path sensitization will work and multiple will not (fault free
O/P->O/P with fault at ckt O/P will be either 1->1 or 0->0, thus not detecting the fault.).