MICROPROCESSOR 8085

LECTURE 24
INTERRUPTS
Sukantho Sikder
 INTERRUPT
S
• Interrupt I/O is a process of data transfer whereby an external device
or a peripheral can inform the processor that it is ready for
communication and it requests attention.
• The process is initiated by an external device and is asynchronous,
meaning it can be initiated at any time without reference to the
system clock.
• However, response to the interrupt request is controlled by
microprocessor.
• Interrupt requests can be classified into two categories:
• Maskable interrupt- Four types of maskable interrupts are there, out of which
one non vectored, three vectored
HARDWARE INTERRUPTS

• TRAP NON-MASKABLE
INTERRUPT
• RST 7.5
VECTORED
• RST 6.5 INTERRUPT
S
• RST 5.5 MASKABLE
INTERRUPTS
• INTR NON VECTORED
INTERRUPT
HARDWARE INTERRUPTS

• TRAP has the highest

TRA priority followed by RST
P 7.5, RST 6.5, RST 5.5 and
RS INTR
7 .5
T 8085 • However, TRAP has a
RST priority than the HOLD
lower
6.5 signal used by DMA.
RST Vectored CALL
5.5 Interrupts Locations
INT
R TRAP 0024 H
RST 7.5 003C H
RST 6.5 0034 H
RST 5.5 002C H
TRA
P
• Non maskable interrupt (NMI).
• It has the highest priority among the interrupt signals.
• It need not be enabled and it cannot be disabled.
• It is level and edge-sensitive, meaning that the input should go HIGH
and stay HIGH to be acknowledged.
• It cannot be acknowledged again until it makes transition from HIGH
to LOW to HIGH.
• When this interrupt is triggered, the program control is transferred to
location 0024 H .
• TRAP is generally used for critical events like power failure
and emergency shut off.
RST 7.5,6.5 AND 5.5

These interrupts are enabled under program control with two

instructions
• EI (Enable Interrupt) and SIM (Set Interrupt Mask)
Set Interrupt Mask (SIM)
Interpretation of the Accumulator bit pattern for the SIM
Bi
instr t 7i o
uct Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
n
SOD SDE XXX R 7.5 MSE M 7.5 M 6.5 M 5.5

Serial SOD
Reset RST 7.M5ask Set RST 7.5
Output Enabled If 1, RST Enable 0=
MASK
data 7.5 is reset available
RST 6.5
off 1 = masked
MASK
RST 5.5
 ENABLE RST 7.5,6.5,5.5 OF 8085
MICROPROCESSOR
The content of the accumulator for instructions SIM to enable RST 7.5, 6.5, 5.5 are
programmed as follows:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOD SDE XXX R 7.5 MSE M 7.5 M 6.5 M 5.5
0 0 0 0 1 0 0 0 =08H

Bits 0,1 and 2 are set to 0 to enable RST 7.5,6.5 and 5.5. Bit 3 is set to make bits 0,1
and 2
effective. Bit 4 is set to 0 to enable RST 7.5 as it is an additional control.
Mnemonics, Operands Comments
EI Enable all interrupts (including INTR)

MVI A,08 Get accumulator bit pattern to enable RST 7.5, 6.5 and 5.5
SIM Enable RST 7.5, 6.5 and 5.5
 ENABLE RST 6.5 AND DISABLE 7.5 AND 5.5

The content of the accumulator to enable RST 6.5 and disable 7.5 and 5.5 are
programmed as follows:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOD SDE XXX R 7.5 MSE M 7.5 M 6.5 M 5.5
0 0 0 1 1 1 0 0 =1D H

Bits 0 and 2 are set to 1 to disable RST 5.5 and 7.5. Bit 3 is set to make bits 0,1 and 2
effective. Bit 4 is set to 1 to disable RST 7.5 as it is an additional control. Bit 3 is set to 1 to
make bits 0,1 and 2 effective.
Mnemonics, Operands Comments
EI Enable all interrupts (including INTR)
MVI A,1D Get accumulator bit pattern to enable RST 7.5, 6.5 and 5.5
SIM Enable RST 7.5, 6.5 and 5.5
 USE RST 7.5 TO INTERRUPT 8085
Memory address Labels Mnemonics, operands Comments
2000 EI Enable all interrupts
2001 MVI A,08 Get accumulator bit pattern to
enable RST 7.5,
6.5 and 5.5
2003 SIM
2004 LOOP LXI H, 3050 Memory address of 1 s t number
2007 MOV A,M Get 1 s t Number
2008 INX H Increment HL pair by
2009 ADD M Add 1 s t and 2 n d number
200A STA 3052 Store result in 3052
200D JMP LOOP Jump to LOOP
This program does a simple addition and continues to do so again and again in a loop.
Now, to interrupt the microprocessor using RST 7.5, we need to apply a pulse to RST
7.5 line. Since, RST 7.5 is vectored interrupt so it will jump to memory location 003C H .
Here, it will get another Jump instruction to the actual Interrupt Service Routine.
USE RST 7.5 TO INTERRUPT 8 0 8 5 - INTERRUPT SERVICE
ROUTINE
003C JMP 5500
Thus, program transfers from memory location 003C to
5500 Interrupt Service Routine at memory location 5500 H
Memory address Labels Mnemonics, operands
Comments
5500 LDA 6500 Get content from 6500 H
5503 STA 7600 Store it in 7600 H
5505 EI Enable Interrupts
5506 RET Return to main program