MICROPROCESSOR 8086

LECTURE 32
8086 MICROPROCESSOR PIPELINED ARCHITECTURE
Sukantho Sikder
ARCHITECTURE OF 8086-INTRODUCTION

• 8086 Contains two independent

functional units: Bus Interface Unit (BIU)
MEMOR
and Execution Unit (EU)
Y
• The BIU handles transfer of data and
addresses between the processor and
BI memory I/O devices.
U • The EU receives opcode of an
instrument from the queue, decodes it
E and then executes it.
U
• While EU is decoding an instruction or
executing an instruction, the BIU
fetches instruction codes from the
memory and stores them in the queue.
• The BIU and EU thus operate in parallel
independently and this type of
PIPELINING IN 8086
Non-pipelined 8085
T1 T2 T3 T4
Fetch 1 Execute 1 Fetch 2 Execute 2

Pipelined 8086
T1 T2 T3 T4
Fetch 1 Execute 1
Fetch 2 Execute 2
Fetch 3 Execute 3
 ARCHITECTURE OF
8086
The Execution
Unit executes
instructions for
the processor
 ARCHITECTURE
8086
OF
When
Can be
addressed as
16-bit register
8 - b i t as
either 8 bit
AX
register
register AL- or
BX
Accumulator
16 bit
low
register
DX
CX
ccumulator
High
ARCHITECTURE OF
8086

The address
Segment compute
registers are used
engine
to converts
address the logical
memory
Internal memory holds the
address
space- that
eitheris held by
RAM,ROM or
Instruction queue
the segment
the I/O spaceregisters
into physical address
BUS INTERFACE UNIT
1 MB
SEGMENTE
D MEMORY

CODE SEGMENT

EXTRA SEGMENT

STACK SEGMENT

DATA SEGMENT