MCS (Morning)

Introduction of Latch and Flip flop

 Combination Logical Circuit
Combination circuit is a type of digital logic which is
implement by boolean circuit where the output is a
pure function of the present input.
 Sequential logic circuit
Sequential logic is a type of logic circuit whose output
depends not only on the present value of its input
signals but on the sequence of past inputs.
Sequence circuit is the extent of combination circuit.
Difference between combination circuit and
sequential circuit
Combination circuit
Output is a function of the
present inputs.
Do not have the ability to store
data (state).
It does not require any feedback.
It simply outputs the input
according to the logic designed.
Independent of clock and hence
does not require triggering to
operate.
Used mainly for Arithmetic and
Boolean operations.
Sequential circuit
Output is a function of clock, present
inputs and the previous states of the
system.
Have memory to store the present
states that is sent as control input
(enable) for the next operation.
It involves feedback from output to
input that is stored in the memory
for the next operation.
Clocked (Triggered for operation
with electronic pulses).
Used for storing data (and hence
used in RAM).
 Note
Combination circuit only work when clock plus is high mean
value 1.
Difference between Synchronous circuit
and Asynchronous circuit
Synchronous circuit change state with every clock
signal, with the state changing according to what the
inputs are.
Synchronous circuit are free from input.
Asynchronous circuits change states whenever the
inputs change.
 Latch And Flip Flop
Latches and flip-flops are the basic elements for storing information.
One latch or flip-flop can store one bit of
information. The main difference between latches and flip-flops is that
for latches, their outputs are constantly
affected by their inputs as long as the enable signal is asserted. In other
words, when they are enabled, their content changes immediately when
their inputs change. Flip-flops, on the other hand, have their content
change only either at the rising or falling edge of the enable signal. This
enable signal is usually the controlling clock signal. After the
rising or falling edge of the clock, the flip-flop content remains constant
even if the input changes. Latch or flip flop are used in ALU Operation,
MUX and DeMUX,
the Counter Circuits, timer etc.
 Note
The first Flip Flop was invented in 1918 by the British
Physicists William Eccles and F.W Jordan
 Types Of Flip Flop
SR Flip Flop
D Flip Flop
JK Flip Flop
T Flip Flop
RS Latch and Clock RS Flip flop
 SR Latch
SR latch has two input S and R.
S stand for Set and R stand for Reset.
SR latch has two output Q and Q’.
Q’ is the complement of the Q output.
S Q

R
Q’

Logical Diagram
RS Latch work only positive edge tagger.
SR Latch Using Nand Gate
 Operation
When S=1 and R=0 then output is Q=0 and Q’=1.
Nand Gate Truth Table
X Y R

0 0 1
0 1 1
1 0 1
1 1 0
 Operation

When S=1 and R=1 then output Q=0 and Q’=1.

 Operation

 When S=o and R=1 then output Q=1 and Q’=0.

 Operation
When S=1 and R=1 then output Q=1 and Q’=0.
 Operation
When S=o and R=0 then output Q=1 and Q’=1.
RS latch with Nor Gate

Diagram Truth Table

 SR Flip Flop
The clocked SR flip flop contain the basic SR latch and
the other two nand gates to provide clock plus.
SR Flip Flop using NAND gate
Q S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 indeter
minate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 indeter
minate

Diagram Truth Table

 Operation
When input S=0 and R=o and Q =0 then output

Q(t+1)= o.
 Operation
When input S=0 and R=1 and Q =0 then output

Q(t+1)= o.
 Operation
When input S=1 and R=0 and Q =0 then output

Q(t+1)= 1.
 Operation
When input S=1 and R=1 and Q =0 then output is

determinate.
 Operation
When input S=0 and R=0 and Q =1 then output is

Q(t+1)=1.
 Operation
When input S=0 and R=1 and Q =1 then output is

Q(t+1)=0.
When input S=1 and R=o and Q =1 then output is

Q(t+1)=1.
When input S=1 and R=1 and Q =1 then output is

Q(t+1)=indeterminate.
 Equation of SR Flip Flop
SR
Q oo o1 11 10
1
0
1 1 1

Q(t+1)=S+QR
RS Flip Flop With NOR Gate
D Flip Flop
 D Flip Flop
D Flip Flop is the modification of the clocked SR flip flop.
In D Flip Flop Inverter is used for second input.
In D flip flop input and output has same value.

Symbolic Diagram
 Note
D Flip Flop is used only to delay the
input value.
D Flip Flop using NAND gate
Q(t) D Q(t+1)

0 0 0
0 1 1
1 0 0
1 1 1
Truth table of D Flip Flop

Diagram of D Flip Flop

 Operation
When Q(t)=0 and input Q=o then output Q(t+1) is

also 0.
 Operation
When Q(t)=0 and input Q=1 then output Q(t+1) is

also 1.
 Operation
When Q(t)=1 and input Q=0 then output Q(t+1) is

also 0.
When Q(t)=1 and input Q=1 then output
Q(t+1) is also 1.
Equation Of D Flip Fop
D 0 1
S 1
0
1 1

Q(t+1)=D
D Flip Flop with NOR and Nor gate
Jk Flip Flop and Jk Master Slave Flip Flop.
 JK Flip Flop
Jk is a refinement of SR Flip Flop to solve the problem
of indeterminate state when both input is ‘1’ .
In JK Flip Flop J and K input work as S and R input.

 JK flip flop using NAND gate

Diagram Truth Table

 Operation
When input J=0 and K=0 and Q=0 then output
Q(t+1)=0.
 Operation
 When input J=0 and K=1 and Q=0 then output Q(t+1)=0.
 Operation
When input J=1 and K=0 and Q=0 then output

Q(t+1)=1.
Operation
When input J=1 and K=1 and Q=0 then output

Q(t+1)=1.
Operation
When input J=0 and K=0 and Q=1 then output

Q(t+1)=1.
Operation
When input J=0 and K=1 and Q=1 then output

Q(t+1)=0.
When input J=1 and K=0 and Q=1 then output
Q(t+1)=1.
Operation
When input J=1 and K=1 and Q=1 then output

Q(t+1)=0.
Equation Of JK Flip Flop
JK 00 01 11 10
Q0 1 1

1 1
1

Q(t+1)=JQ’+ QK’
JK flip flop with NOR Gate
 T Flip Flop Using NAND gate
It’s a single input version of JK flip flop.
T stand for toggle.
T Flip Flop has one input and and two output.

A

A

(a) Diagram
 T Flip Flop

Operation Truth Table

 If Q=0 and input T=o then output Q(t+1)=o.
 If Q=0 and input T=1 then output Q(t+1)=1.
 If Q=1 and input T=o then output Q(t+1)=1.
 If Q=1 and input T=1 then output Q(t+1)=o.
 K-Map Equation
Q T
T Flip Flop with NOR gate
 Master Slave Flip Flop
MASTER Slave Flip Flop can be constructed by
using two JK flip flop .
The first flip flop is called the Master and the second
flip flop is called slave.
Master flip flop is driven by positive clock and slave flip
flop is driven by negative clock.
 Master Slave Flip Flop
During positive clock master flip flop given output but
slave flip flop does not response.
During negative clock master flip flop does not
response but slave flip flop given output .