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Introduction
• Most of the real time parameters are analog in nature such as pressure,
temperature, speed, velocity, mass etc.
• All the communication and electronic applications are migrating to
digital techniques.
• The devices used bridge between analog parameters such as continues
voltage or current and binary based devices such as computer, digital
ICs, are termed as analog to digital converters.
• The real time parameters are first converted to current to voltage using
transducers and the output of transducer is given as the input to the ADC
to obtain binary digital values proportional to real time parameters.
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Analog to Digital Converter
•
• - Analog input
• Integrating type
– Single Slope ADC
– Dual Slope ADC
– Adaptive DM (ADM)
– Sigma – Delta (∑ - ∆)
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Flash Type ADC
• This type of ADC is also called as
simultaneous type (or) parallel comparator
ADC (or) simply, comparator type.
• This type of ADC is the fastest of all ADCs
and expensive type too.
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Circuit Diagram Flash Type ADC
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•• The
circuits consists of comparators (7 comparators when n=3 and
• Note that the analog input is applied to non inverting terminal of all
will be switched ON or OFF and note that if any comparator is ON, all
• The greatest advantage of this type is the speed in the range of 100ns or
even less.
• “Flash” is the name dedicated to speed. Its accuracy and input hold time
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• The
• heart of the circuits is a 8 bit successive approximation register (SAR). Initially the content of 8 bit
SAR is MSB only binary stream (10000000). It is given to a 8 bit DAC which in turn produces the
Now
• This known analog voltage is compared with unknown Analog input . If >,the comparator is switched ON
• On the other hand, if ,the comparator is switched O (+) and MSB bit position is inverted (Logic 0).
• On the next block pulse, SAR sets next bit position and D/A converted produces a corresponding analog
• This voltage is then compared with to decide whether the bit should be 1 or 0. Likewise, the comparison
• The conversion complete signal is arrived from SAR which also acts as the enable line E for the 8 bit latch.
The 8 bit latch finally provides the digital data output proportional to
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Advantage
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Integrating Type ADC
• The basic principle of integrating type ADC is to compare
the unknown analog input voltage with reference voltage
that begins at 0V and increase linearly with time.
• A ramp generator or integrator is used here.
• It can be classified into two types
– Single Slope ADC
– Dual Slope ADC
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Single Slope ADC
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•• A unknown analog input is given to the non inverting input of comparator.
• At the same time ramp reset is given to ramp generator. Thereafter, the ramp
• Let us assume that ramp generator produces a ramp up to 1V for every 1ms.
• This allows the clock input to pass through the AND gate and the counter
starts counting.
• The output of the comparator is also given to timing and control unit which
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•• Now
1 V is compared with and if input again the
comparator switches ON allowing the clock to the counter
to countup.
• This process continues and for each and every 1ms of time,
the ramp generator is incremented by 1V.
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• Now, the counter stops and timing and control
unit issues a Latch/Strobe input to latches.
• The latches just switches the counted value to
the decoders or driver.
• The output of the driver a 7 segment LED
display. The display shows a digital value
equivalent to unknown analog input.
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Disadvantage
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Dual Slope ADC
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•• time
is known and is unknown (not a predetermined
time). Slope at is unknown but slope at is unknown.
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•• Assume
a 4 bit decade counter initialized to 0000.
• Ramp output is set to 0V.
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•• So
clock passes through AND gate to the counter. The
negative ramp will proceed for the fixed time period
which is determined by the counts of counter.
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•• The
output of the integrator is now positive and rams up till 0 volt which is other
input to comparator. The comparator produces not allowing the clock to enter the
counter. The positive voltage is.
• This type of ADC is the most widely used ADC and more suitable for slowly
varying signals as input. Slow speed, High accuracy, & input hold time with high
resolution
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ADC using Voltage to Time Conversion
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•
• is the reference voltage and it is negative.
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•• The
negative reference voltage is applied to integrators inverting
input.
• The output of integrator ramps up and compares with unknown
analog input sample (derived from S/H circuit)
• When , the comparator output is positive. During this time, is low
thus allowing the clock voltage ( to appear at CL input of counter.
• Counter starts counting till is greater than .
• When <, is negative. So cannot reach the CL input of high speed
counter. At the same time is high, the clock cannot enter the AND
gate.
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•
• is ON only for a period of
• is OFF for the period of during which the
counter counts.
• Whenever is at sampling time the switch ‘S’
closes and discharges the capacitor..
• During the switch Open allowing charging.
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•
• - Sampling Period and =
• - Sampling time
• - Holding Time
• - Input voltage
• - Control Voltage
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Oversampling A to D Converters
•
• This type of ADC samples analog signal at the
rate much higher than the required sampling
rate ().
• The typical sampling rate is 16,32, or 64 times
of original sampling rate.
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Delta Modulation
• Delta modulation (DM) developed in the 1940s is a differential pulse code modulation (DPCM) techniques
• When signal variations between the subsequent sample periods are very small, the word length of the
• With very high over sampling rates, the changes between sample periods are made very small, and
• With delta modulation, rather than transmit a coded representation of the sample, only a single bit is
transmitted, which simply indicates whether that sample is larger or smaller than the previous sample.
• If the current sample is smaller than the previous sample, a logic 0 is transmitted.
• If the current sample is larger than the previous sample, a logic 1 is transmitted.
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• The i/p analog is sampled and converted to a PAM signal.
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• Initially up-down converter is zeroed.
• This is indicating current sample is larger in amplitude than the previous sample.
• DAC o/p voltage is equal to the magnitude of the minimum step size.
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Slope Overload
• The analog input signal changes at a faster rate than the DAC can maintain. The slope of the analog
signal is greater than the delta modulator can maintain and is called slope overload.
Prevention:
• Large resolution.
• Slope overload is more prevalent in analog signals that have steep slopes or whose amplitudes vary
rapidly.
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Granular Noise
• When the original analog input signal has relatively constant amplitude, the
reconstructed signal has variations that were not present in the original signal, is called
granular noise.
Prevention:
• Small resolution
• Granular noise is more prevalent in analog signals that have gradual slopes and whose