SOC Verification with

System Verilog

Ramdas M
Expert Verification Engineer

Verification with System Verilog 05/04/202 1

1
 Introduction - Course

▪ This course teaches

▪ System on Chip (SOC) design verification concepts

(Section 2)

▪ Coding in System Verilog language for verification

(Section 3-6)

Verification with System Verilog 05/04/202 2

1
Course Goal / Take away

▪ Learn important concepts in SOC/ASIC/VLSI

design verification

▪ Be able to code, simulate and verify in System

Verilog language

▪ Be ready and qualified for a Verification ready job !!

Verification with System Verilog 05/04/202 3

1
Intended Audience

▪ Students
▪ VLSI and Digital Design
▪ Micro Electronics
▪ Embedded Systems Design
▪ Work professionals
▪ VLSI Design Professionals
▪ Verification Engineers

Verification with System Verilog 05/04/202 4

1
Prerequisites

▪ General Awareness of
▪ Digital or Logic design flows
▪ Some programming language
▪ Passion for Learning

Verification with System Verilog 05/04/202 5

1
Teaching Methods

▪ Short Video Lectures

▪ Power point and white board screen captures
▪ Coding Exercises after few lectures
▪ Quizzes at end of sections

Verification with System Verilog 05/04/202 6

1
 Exercises at end of sections
▪ Exercise 1: Case Study on How to verify a design?
▪ Exercise 2: Coding a Design to be Verified.
▪ Exercise 3: Coding Interfaces and Clocking Blocks
▪ Exercise 4: Coding Test bench components
▪ Exercise 5: Randomizing your stimulus generation
▪ Exercise 6: Creating a Test using Threads
▪ Exercise 7: Simulating and Verifying all together

Verification with System Verilog 05/04/202 7

1