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2019-08 Bit2133 Notes 1567655338 l2
2019-08 Bit2133 Notes 1567655338 l2
Outline
• Computer Components
• Computer Function
• Interconnection Structure
• Computer Memory
• Bus Interconnection
• PCI
• Program Concept
• What is Program
• Processor-memory
• Processor -I/O
• Data processing
• Control
• Combination of the above
• Computers
employ a
fetch-decode-
execute cycle
to run
programs as
follows . . .
10
Fetch-decode-execute
11
Fetch-decode-execute
12
Fetch-decode-execute
13
Fetch-decode-execute
14
Example of Program Execution
• Memory-to-Processor
• Processor-to-Memory
• I/O-to-Processor
• Processor-to-I/O
• I/O-to-or-from-Memory
• Memory Location
• Memory Capacity
• Internal
• External
• Addressable unit
• Sequential
• Direct
• Random
• Associative
• Registers
• Internal or Main memory
• External memory
• Access time
• Memory Cycle time
• Transfer Rate
• Semiconductor
• Magnetic
• Optical
• Others
• Communication pathway
• Usually broadcast
• Often grouped
• Power lines may not be shown
• Data Bus
– Carries data
– Width is a key determinant of performance
• Address Bus
– Identify the source or destination of data
– Bus width determines maximum memory capacity
• Control Bus
– Control and timing information
• Dedicated
– Separate data & address lines
• Multiplexed
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
BTECH 2306 Computer Architecture 51
Bus Arbitration
• Centralised
– Single hardware device controlling bus access
– May be part of CPU or separate
• Distributed
– No central controller
– Each module may claim the bus
• Synchronous Timing
– Events determined by clock signals
– Control Bus includes clock line
– A single 1-0 is a bus cycle
– All devices can read clock line
– Usually sync on leading edge
– Usually a single cycle for an event
• Asynchronous Timing
– The occurrence of one event on a bus follows and depends
on the occurrence of a previous event.
• Systems lines
• Address & Data
• Interface Control
• Arbitration
• Error lines
• Interrupt lines
• Cache support
• 64-bit Bus Extension
• JTAG/Boundary Scan