Lecture 2

Outline

• Computer Components
• Computer Function
• Interconnection Structure
• Computer Memory
• Bus Interconnection
• PCI

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Program

• Program Concept
• What is Program

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Function of Control Unit

• For each operation a unique code is provided

• A hardware segment accepts the code and
issues the control signals

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 Components - CPU

• Control Unit and the Arithmetic and Logic

Unit constitute the Central Processing Unit.
• Data and instructions need to get into the
system and results out
• Temporary storage of code and results is
needed
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Computer Components: Top Level View

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Instruction Cycle

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Fetch Cycle
• PC holds address of next instruction to fetch
• Processor fetches instruction from memory location
pointed to by PC
• Increment PC
• Instruction loaded into IR
• Processor interprets instruction and performs required
actions
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Execute Cycle

• Processor-memory
• Processor -I/O
• Data processing
• Control
• Combination of the above

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 Fetch-decode-execute

• Computers
employ a
fetch-decode-
execute cycle
to run
programs as
follows . . .

10
 Fetch-decode-execute

• The control unit fetches the next instruction from memory

using the program counter to determine where the
instruction is located.

11
Fetch-decode-execute

• The instruction is decoded into a language that the ALU

can understand.

12
Fetch-decode-execute

• Any data operands required to execute the instruction are

fetched from memory and placed into registers within the
CPU.

13
Fetch-decode-execute

• The ALU executes the instruction and places results in

registers or memory.

14
Example of Program Execution

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Instruction Cycle State Diagram

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Instruction Cycle State

• Instruction Address Calculation (iac)

• Instruction Fetch (if)
• Instruction Operation Decoding (iod)

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Instruction Cycle State

• Operand Address Calculation (oac)

• Operand fetch (of)
• Data Operation (do)
• Operand Store (os)

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Interrupts

• Mechanism by which other modules (e.g. I/O)

may interrupt normal sequence of processing.
• Interrupts are provided as a way to improve
processing efficiency .

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Classes of Interrupts
• Program – instruction execution – overflow,
division by 0, segmentation fault
• Timer – internal processor timer – processing
on time intervals
• I/O – I/O controller – normal operation
completion, error condition
• Hardware failure – power failure, memory
parity error

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Program Flow Control

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Interrupt Cycle

• Added to instruction cycle

• Processor checks for interrupt
• If no interrupt, fetch next instruction
• If interrupt pending:

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Instruction Cycle with Interrupts

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Instruction Cycle (with Interrupts) -
State Diagram

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 Multiple Interrupts
• Disable interrupts while an interrupt is being
processed
• Define priorities for interrupts
– Low priority interrupts can be interrupted by high
priority interrupts
– Low priority interrupt is returned to after high priority
interrupt has been processed

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Multiple Interrupts - Sequential

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Multiple Interrupts - Nested

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Computer Modules

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Computer Module

• Memory-to-Processor
• Processor-to-Memory
• I/O-to-Processor
• Processor-to-I/O
• I/O-to-or-from-Memory

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Memory

• Memory Location
• Memory Capacity

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Memory (Unit of Transfer)

• Internal
• External
• Addressable unit

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Memory (Access Methods)

• Sequential
• Direct

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Memory (Access Methods)

• Random
• Associative

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Memory Hierarchy

• Registers
• Internal or Main memory
• External memory

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Memory Hierarchy

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Performance

• Access time
• Memory Cycle time
• Transfer Rate

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Physical Types

• Semiconductor
• Magnetic
• Optical
• Others

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Memory Connection

• Receives and sends data

• Receives addresses (of locations)
• Receives control signals

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Input/Output Connection

• Similar to memory from computer’s viewpoint

• Output
• Input

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Input/Output Connection

• Receive control signals from computer

• Send control signals to peripherals
• Receive addresses from computer
• Send interrupt signals (control)

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CPU Connection

• Reads instruction and data

• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts

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What is a Bus?

• Communication pathway
• Usually broadcast
• Often grouped
• Power lines may not be shown

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Buses

• There are number of possible interconnection

systems
• Single and multiple BUS structures are most
common

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Bus

• Data Bus
– Carries data
– Width is a key determinant of performance

• Address Bus
– Identify the source or destination of data
– Bus width determines maximum memory capacity

• Control Bus
– Control and timing information

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Bus Interconnection Scheme

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What do Buses look like?

• Parallel lines on circuit boards

• Ribbon cables
• Strip connectors on mother boards
• Sets of wires

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Physical Realization of Bus
Architecture

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Single Bus Problem

• Lots of devices on one bus leads to:

– Propagation delays
• Most systems use multiple buses to overcome
these problems.

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Traditional ISA with Cache

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High Performance Bus

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Bus Types

• Dedicated
– Separate data & address lines

• Multiplexed
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
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 Bus Arbitration

• More than one module controlling the bus

• Only one module may control bus at one time
• Arbitration may be centralised or distributed

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Centralised or Distributed Arbitration

• Centralised
– Single hardware device controlling bus access
– May be part of CPU or separate

• Distributed
– No central controller
– Each module may claim the bus

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Timing

• Synchronous Timing
– Events determined by clock signals
– Control Bus includes clock line
– A single 1-0 is a bus cycle
– All devices can read clock line
– Usually sync on leading edge
– Usually a single cycle for an event

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Synchronous Timing Diagram

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Timing

• Asynchronous Timing
– The occurrence of one event on a bus follows and depends
on the occurrence of a previous event.

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Asynchronous Timing – Read Diagram

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Asynchronous Timing – Write Diagram

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PCI Bus

• Peripheral Component Interconnection

• High-bandwidth, processor independent bus
• Intel released to public domain
• 32 or 64 bit
• 50 lines

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PCI Bus Lines (required)

• Systems lines
• Address & Data
• Interface Control
• Arbitration
• Error lines

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PCI Bus Lines (Optional)

• Interrupt lines
• Cache support
• 64-bit Bus Extension
• JTAG/Boundary Scan

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