Digital Design: An Embedded Systems Approach Using Verilog: Sequential Basics

Digital Design:
An Embedded Systems
Approach Using Verilog
Chapter 4
Sequential Basics
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
Verilog
Sequential Basics
 Sequential circuits
 Outputs depend on current inputs and
previous inputs
 Store state: an abstraction of the history of
inputs
 Usually governed by a periodic clock
signal
Digital Design — Chapter 4 — Sequential Basics 2

Verilog
D-Flipflops
 1-bit storage element
 We will treat it as a basic component
clk
D Q
D
clk
Q
 Other kinds of flipflops

 SR (set/reset), JK, T (toggle)

Verilog
Registers
 Store a multi-bit encoded value
 One D-flipflop per bit
 Stores a new value on d (0 ) D Q q (0 )
each clock cycle clk
d (1 ) D Q q (1 )
wire [n:0] d; clk
reg [n:0] q;
event list
…
...
d (n) D Q q (n)
always @(posedge clk) clk clk
q <= d;
n n
D Q
nonblocking
clk
asignment
Verilog
Pipelines Using Registers

Total delay = Delay1 + Delay2 + Delay3
Interval between outputs > Total delay
combin- combin- combin-

d _in ational ational ational
circuit 1 circuit 2 circuit 3
combin- combin- combin-

d _in D Q D Q D Q d _o u t
ational ational ational
clk clk clk
circuit 1 circuit 2 circuit 3
clk
Clock period = max(Delay1, Delay2, Delay3)

Total delay = 3 × clock period
Interval between outputs = 1 clock period
Verilog
Pipeline Example
 Compute the average of corresponding
numbers in three input streams
 New values arrive on each clock edge
module average_pipeline ( output reg signed [5:-8] avg,

input signed [5:-8] a, b, c,
input clk );
wire signed [5:-8] a_plus_b, sum, sum_div_3;

reg signed [5:-8] saved_a_plus_b, saved_c, saved_sum;
...

Verilog
Pipeline Example
...
assign a_plus_b = a + b;
always @(posedge clk) begin // Pipeline register 1
saved_a_plus_b <= a_plus_b;
saved_c <= c;
end
assign sum = saved_a_plus_b + saved_c;
always @(posedge clk) // Pipeline register 2
saved_sum <= sum;
assign sum_div_3 = saved_sum * 14'b00000001010101;
always @(posedge clk) // Pipeline register 3
avg <= sum_div_3;
endmodule

Verilog
D-Flipflop with Enable

 Storage controlled by a clock-enable
 stores only when CE = 1 on a rising edge
of the clock
clk
D Q
CE
CE
clk D
 CE is a synchronous control input

Verilog
Register with Enable

 One flipflop per bit
 clk and CE wired in common
wire [n:0] d;
wire ce;
reg [n:0] q;
...
always @(posedge clk)

if (ce) q <= d;

Verilog
Register with Synchronous Reset

 Reset input forces stored value to 0
 reset input must be stable around rising
edge of clk
1 2 3 4 5 6 7 8
clk
D Q re s e t
CE
CE
re s e t
clk D
Q

if (reset) q <= 0;
else if (ce) q <= d;
Verilog
Register with Asynchronous Reset

 Reset input forces stored value to 0
 reset can become 1 at any time, and effect
is immediate
 reset should return to 0 synchronously
1 2 3 4 5 6 7 8
clk
D Q
re s e t
CE
re s e t CE
clk D
Q

Verilog
Asynch Reset in Verilog
always @(posedge clk or posedge reset)

if (reset) q <= 0;
else if (ce) q <= d;
 reset is an asynchronous control input here

 include it in the event list so that the process
responds to changes immediately

Verilog
Example: Accumulator
 Sum a sequence of signed numbers
 A new number arrives when data_en = 1
 Clear sum to 0 on synch reset
module accumulator
( output reg signed [7:-12] data_out,
input signed [3:-12] data_in,
input data_en, clk, reset );
wire signed [7:-12] new_sum;
assign new_sum = data_out + data_in;
if (reset) data_out <= 20'b0;
else if (data_en) data_out <= new_sum;
endmodule
Verilog
Flipflop and Register Variations
module flip_flop_n ( output reg Q,

output Q_n,
input pre_n, clr_n, D,
input clk_n, CE );
p re always @( negedge clk_n or

negedge pre_n or negedge clr_n ) begin
D Q if ( !pre_n && !clr_n)
CE $display("Illegal inputs: pre_n and clr_n both 0");
clk Q if (!pre_n) Q <= 1'b1;
clr else if (!clr_n) Q <= 1'b0;
else if (CE) Q <= D;
end
assign Q_n = ~Q;
endmodule

Verilog
Shift Registers
 Performs shift operation on stored data
 Arithmetic scaling
Serial transfer
0
 D(n –1 ) 1
D Q Q(n –1 )
CE
of data clk
0
D Q Q(n –2 )
D(n –2 ) 1
CE
D_in clk
D Q
lo ad _e n
CE
clk
0
D Q Q(0 )
D(0 ) 1
CE
lo a d _e n
CE clk
clk

Verilog
Example: Sequential Multiplier

 16×16 multiply over 16 clock cycles, using
one adder
 Shift register for multiplier bits
 Shift register for lsb’s of accumulated product
1 6 -b it
s h ift re g
D_in
y(1 5 ...0 ) D Q 0
y_lo a d _e n lo ad _e n 1 6 -b it 1 7 -b it re g 3 1 ...1 6
ad d e r
y_ce CE 16 D Q 15
P(3 1 ...1 5 )
clk x c1 6
re s e t
y CE
1 5 ...0
1 6 -b it re g c0 s clk
x (1 5 ...0 ) D Q
x _ce CE
1 5 -b it
clk s h ift re g
D_in Q P(1 4 ...0 )
P_re s e t
P_ce CE
clk clk

Verilog
Latches
 Level-sensitive storage
 Data transmitted while enable is '1'
 transparent latch
 Data stored while enable is '0'
LE
D Q
D
LE
Q

Verilog
Feedback Latches
 Feedback in gate circuits produces
latching behavior
 Example: reset/set (RS) latch
+V
R
S Q
Q
R Q
S
 Current RTL synthesis tools don’t accept

Verilog models with unclocked feedback
Verilog
Latches in Verilog
 Latching behavior is usually an error!
always @*
if (~sel) begin
z1 <= a1; z2 <= b1;
end
else begin Oops!
z1 <= a2; z3 <= b2; Should be
end z2 <= ...
 Values must be stored

 for z2 while sel = 1
 for z3 while sel = 0
Verilog
Counters
 Stores an unsigned integer value
 increments or decrements the value
 Used to count occurrences of
 events
 repetitions of a processing step
 Used as timers
 count elapsed time intervals by
incrementing periodically

Verilog
Free-Running Counter
+1 D Q Q
clk
clk
 Increments every rising edge of clk

 up to 2n–1, then wraps back to 0
 i.e., counts modulo 2n
 This counter is synchronous
 all outputs governed by clock edge

Verilog
Example: Periodic Control Signal

 Count modulo 16 clock cycles
 Control output = 1 every 8th and 12th cycle
 decode count values 0111 and 1011
0 0
D Q
clk
1 1
D Q
clk
+1 ctrl
2 2
D Q
clk
3 3
D Q
clk
clk

Verilog
Example: Periodic Control Signal
module decoded_counter ( output ctrl,

input clk );
reg [3:0] count_value;
count_value <= count_value + 1;
assign ctrl = count_value == 4'b0111 ||
count_value == 4'b1011;
endmodule

Verilog
Count Enable and Reset

 Use a register with control inputs
+1
D Q Q
CE CE
re s e t re s e t
clk clk
 Increments when CE = 1 on rising clock

edge
 Reset: synch or asynch
Verilog
Terminal Count
 Status signal indicating final count value
co u n te r
Q0
Q1 TC
…
…
…
clk Qn
 TC is 1 for one cycle in every 2n cycles

 frequency = clock frequency / 2n
 Called a clock divider
Verilog
Divider Example
 Alarm clock beep: 500Hz from 1MHz clock
1 0 -b it
co u n te r
co u n t
Q D Q to n e
to n e 2
clk TC CE
clk
clk
clk
co u n t 0 1 2 0 1 2 0 1 2 0 1
1023 1023 1023
to n e 2
to n e

Verilog
Divide by k
 Decode k–1 as terminal count and reset
counter register
 Counter increments modulo k
 Example: decade counter
 Terminal count = 9
co u n te r
clk clk Q0 Q0
Q1 Q1
Q2 Q2
re s e t Q3 Q3

Verilog
Decade Counter in Verilog
module decade_counter ( output reg [3:0] q,

input clk );
q <= q == 9 ? 0 : q + 1;
endmodule

Verilog
Down Counter with Load

 Load a starting value, then decrement
 Terminal count = 0
 Useful for interval timer
–1 0
D Q Q
1
D clk
lo a d =0 ? TC
clk

Verilog
Loadable Counter in Verilog
module interval_timer_rtl ( output tc,

input [9:0] data,
input load, clk );
reg [9:0] count_value;
if (load) count_value <= data;
else count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule

Verilog
Reloading Counter in Verilog

module interval_timer_repetitive ( output tc,
input [9:0] data,
input load, clk );
reg [9:0] load_value, count_value;
if (load) begin
load_value <= data;
count_value <= data;
end
else if (count_value == 0)
count_value <= load_value;
else
count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule

Verilog
Ripple Counter
 Each bit toggles between 0 and 1
clk clk Q Q0
D Q
 when previous bit changes from 1 to 0
clk Q Q1 clk
D Q
Q0
clk Q Q2 Q0
D Q
Q1
Q1
clk Q Qn Q2
D Q
Q2

Verilog
Ripple or Synch Counter?

 Ripple counter is ok if
 length is short
 clock period long relative to flipflop delay
 transient wrong values can be tolerated
 area must be minimal
 E.g., alarm clock
 Otherwise use a synchronous counter

Verilog
Datapaths and Control

 Digital systems perform sequences of
operations on encoded data
 Datapath
 Combinational circuits for operations
 Registers for storing intermediate results
 Control section: control sequencing
 Generates control signals
 Selecting operations to perform
 Enabling registers at the right times
 Uses status signals from datapath
Verilog
Example: Complex Multiplier

 Cartesian form, fixed-point
 operands: 4 pre-, 12 post-binary-point bits
 result: 8 pre-, 24 post-binary-point bits
 Subject to tight area constraints
a  ar  jai b  br  jbi
p  ab  pr  jpi  (ar br  ai bi )  j (ar bi  ai br )
 4 multiplies, 1 add, 1 subtract
 Perform sequentially using 1 multiplier, 1
adder/subtracter
Verilog
Complex Multiplier Datapath
a _r 0
D Q D Q p _r
a _i 1 CE CE
a _s e l × clk ± clk
b _r 0
b _i 1
D Q D Q p _i
b _s e l CE CE
p p 1 _ce
p p 2 _ce clk clk
sub
p _r_ce
p _i_ce
clk

Verilog
Complex Multiplier in Verilog

module multiplier
( output reg signed [7:-24] p_r, p_i,
input signed [3:-12] a_r, a_i, b_r, b_i,
input clk, reset, input_rdy );
reg a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce;
wire signed [3:-12] a_operand, b_operand;
wire signed [7:-24] pp, sum
reg signed [7:-24] pp1, pp2;
...

Verilog
Complex Multiplier in Verilog

assign a_operand = ~a_sel ? a_r : a_i;
assign b_operand = ~b_sel ? b_r : b_i;
assign pp = {{4{a_operand[3]}}, a_operand, 12'b0} *
{{4{b_operand[3]}}, b_operand, 12'b0};
always @(posedge clk) // Partial product 1 register
if (pp1_ce) pp1 <= pp;
always @(posedge clk) // Partial product 2 register
if (pp2_ce) pp2 <= pp;
assign sum = ~sub ? pp1 + pp2 : pp1 - pp2;
always @(posedge clk) // Product real-part register
if (p_r_ce) p_r <= sum;
always @(posedge clk) // Product imaginary-part register
if (p_i_ce) p_i <= sum;
...
endmodule

Verilog
Multiplier Control Sequence

 Avoid resource conflict
 First attempt
1. a_r * b_r → pp1_reg
2. a_i * b_i → pp2_reg
3. pp1 – pp2 → p_r_reg
4. a_r * b_i → pp1_reg
5. a_i * b_r → pp2_reg
6. pp1 + pp2 → p_i_reg
 Takes 6 clock cycles

Verilog
Multiplier Control Sequence

 Merge steps where no resource conflict
 Revised attempt
1. a_r * b_r → pp1_reg
2. a_i * b_i → pp2_reg
3. pp1 – pp2 → p_r_reg
a_r * b_i → pp1_reg
4. a_i * b_r → pp2_reg
5. pp1 + pp2 → p_i_reg
 Takes 5 clock cycles
Verilog
Multiplier Control Signals
Step a_sel b_sel pp1_ce pp2_ce sub p_r_ce p_i_ce
1 0 0 1 0 – 0 0
2 1 1 0 1 – 0 0
3 0 1 1 0 1 1 0
4 1 0 0 1 – 0 0
5 – – 0 0 0 0 1

Verilog
Finite-State Machines
 Used the implement control sequencing
 Based on mathematical automaton theory
 A FSM is defined by
 set of inputs: Σ
 set of outputs: Γ
 set of states: S
 initial state: s0  S
 transition function: δ: S × Σ → S
 output function: ω: S × Σ → Γ or ω: S → Γ
Verilog
FSM in Hardware
cu rre n t_s ta t e next

D Q
s tate
re s e t re s e t lo g ic
clk clk
o u tp u t
lo g ic o u tp u t s
in p u ts
Mealy FSM
only
 Mealy FSM: ω: S × Σ → Γ
 Moore FSM: ω: S → Γ
Verilog
FSM Example: Multiplier Control

Transition function
 One state per step
current_ input_ next_
 Separate idle state? state rdy state
 Wait for input_rdy = 1
step1 0 step1
 Then proceed to steps 1, 2, ...
 But this wastes a cycle! step1 1 step2
 Use step 1 as idle state
step2 – step3
 Repeat step 1 if input_rdy ≠ 1
 Proceed to step 2 otherwise step3 – step4
 Output function step4 – step5
 Defined by table on slide 43
 Moore or Mealy? step5 – step1

Verilog
State Encoding
 Encoded in binary
 N states: use at least log2N bits
 Encoded value used in circuits for transition
and output function
 encoding affects circuit complexity
 Optimal encoding is hard to find
 CAD tools can do this well
 One-hot works well in FPGAs
 Often use 000...0 for idle state
 reset state register to idle
Verilog
FSMs in Verilog
 Use parameters for state values
 Synthesis tool can choose an alternative
encoding
parameter [2:0] step1 = 3'b000, step2 = 3'b001,

step3 = 3'b010, step4 = 3'b011,
step5 = 3'b100;
reg [2:0] current_state, next_state ;
...

Verilog
Multiplier Control in Verilog

always @(posedge clk or posedge reset) // State register
if (reset) current_state <= step1;
else current_state <= next_state;
always @* // Next-state logic
case (current_state)
step1: if (!input_rdy) next_state = step1;
else next_state = step2;
step2: next_state = step3;
endcase

Verilog
Multiplier Control in Verilog

always @* begin // Output_logic
a_sel = 1'b0; b_sel = 1'b0; pp1_ce = 1'b0; pp2_ce = 1'b0;
sub = 1'b0; p_r_ce = 1'b0; p_i_ce = 1'b0;
case (current_state)
step1: begin
pp1_ce = 1'b1;
end
step2: begin
a_sel = 1'b1; b_sel = 1'b1; pp2_ce = 1'b1;
end
step3: begin
b_sel = 1'b1; pp1_ce = 1'b1;
sub = 1'b1; p_r_ce = 1'b1;
end
step4: begin
a_sel = 1'b1; pp2_ce = 1'b1;
end
step5: begin
p_i_ce = 1'b1;
end
endcase
end

Verilog
State Transition Diagrams

 Bubbles to represent states
 Arcs to represent transitions
0, 0
 Example 0, 1
 S = {s1, s2, s3} s1
1, 0
s2
 Inputs (a1, a2):
Σ = {(0,0), (0,1), (1,0), (1,1)} 1, 1
 δ defined by diagram 0, 0
s3 0, 1
1, 1
1, 0

Verilog
State Transition Diagrams

 Annotate diagram to
define output 0, 1 / 0, 1, 1
function
s1 1, 0 / 1, 0, 0 s2
 Annotate states for 0, 0 / 0, 0, 0
1, 0 0, 0
Moore-style outputs
Annotate arcs for
1, 1 / 1, 1, 1
 / 0, 1, 1
Mealy-style outputs
 Example 0, 0 / 0, 0, 0
s3 0, 1 / 0, 1, 1
 x1, x2: Moore-style 0, 1
1, 1 / 1, 1, 1
 y1, y2, y3: Mealy-style 1, 0 / 1, 0, 0

Verilog
Multiplier Control Diagram

 Input: input_rdy
 Outputs
 a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce
s te p 1 1 s te p 2
0
0 , 0 , 1 , 0 , –, 0 , 0 1 , 1 , 0 , 1 , –, 0 , 0
s te p 5 s te p 4 s te p 3
–, –, 0 , 0 , 0 , 0 , 1 1 , 0 , 0 , 1 , –, 0 , 0 0, 1, 1, 0, 1, 1, 0

Verilog
Bubble Diagrams or Verilog?

 Many CAD tools provide editors for
bubble diagrams
 Automatically generate Verilog for
simulation and synthesis
 Diagrams are visually appealing
 but can become unwieldy for complex
FSMs
 Your choice...
 or your manager's!

Verilog
Register Transfer Level

 RTL — a level of abstraction
 data stored in registers
 transferred via circuits that operate on data
outputs
inputs
control section

Verilog
Clocked Synchronous Timing

 Registers driven by a common clock
 Combinational circuits operate during clock
cycles (between rising clock edges)
tc
clk
tco Q1 tpd D2 tsu tco
Q1
tpd t tsu
tco + tpd + tsu < tc D2

Verilog
Control Path Timing
tco tsu tco + tpd-s + tpd-o + tpd-c + tsu < tc

tpd-s tpd-c
tco + tpd-s + tpd-ns + tsu < tc

tpd-o
tpd-ns
tsu Ignore tpd-s for a Moore FSM

Verilog
Timing Constraints
 Inequalities must hold for all paths
 If tco and tsu the same for all paths
 Combinational delays make the difference
 Critical path
 The combinational path between registers with
the longest delay
 Determines minimum clock period for the entire
system
 Focus on it to improve performance
 Reducing delay may make another path critical

Verilog
Interpretation of Constraints
1. Clock period depends on delays
 System can operate at any frequency up
to a maximum
 OK for systems where high performance
is not the main requirement
2. Delays must fit within a target clock
period
 Optimize critical paths to reduce delays if
necessary
 May require revising RTL organization

Verilog
Clock Skew
clk1
Q1
Q1 D2
clk2
th
D2
 Need to ensure clock edges arrive at all

registers at the same time
 Use CAD tools to insert clock buffers and
route clock signal paths
Verilog
Off-Chip Connections
 Delays going off-chip and inter-chip
 Input and output pad delays, wire delays
 Same timing rules apply
 Use input and output registers to avoid
adding external delay to critical path
Q1 D2

Verilog
Asynchronous Inputs
 External inputs can change at any time
 Might violate setup/hold time constraints
 Can induce metastable state in a flipflop
0 1 0 1
Unbounded time to recover

k 2t
 e
MTBF 
 May violate setup/hold time k1 f f f 2
of subsequent flipflop k 2 0
Verilog
Synchronizers
s yn ch _in
a s yn ch _in D Q D Q
clk clk
clk
 If input changes outside setup/hold window

 Change is simply delayed by one cycle
 If input changes during setup/hold window
 First flipflop has a whole cycle to resolve
metastability
 See data sheets for metastability parameters
Verilog
Switch Inputs and Debouncing

 Switches and push-buttons suffer from
contact bounce
 Takes up to 10ms to settle
 Need to debounce to avoid false triggering
+V
 Requires two inputs
R and two resistors
 Must use a break-
before-make double-
S Q
throw switch
Verilog
Switch Inputs and Debouncing

 Alternative
 Use a single-throw switch
 Sample input at intervals longer than bounce time
 Look for two successive samples with the same
value
+V
 Assumption
 Extra circuitry inside the chip
is cheaper than extra
components and connections
outside

Verilog
Debouncing in Verilog
module debouncer ( output reg pb_debounced,
input pb,
input clk, reset );
reg [18:0] count500000; // values are in the range 0 to 499999
wire clk_100Hz;
reg pb_sampled;
always @(posedge clk or posedge reset)
if (reset) count500000 <= 499999;
else if (clk_100Hz) count500000 <= 499999;
else count500000 <= count500000 - 1;
assign clk_100Hz = count500000 == 0;
if (clk_100Hz) begin
if (pb == pb_sampled) pb_debounced <= pb;
pb_sampled <= pb;
end
endmodule

Verilog
Verifying Sequential Circuits

Verification Testbench
Design Under
Verification
(DUV)
Apply
Test Cases Checker
 DUV may take multiple and varying number of

cycles to produce output
 Checker needs to
 synchronize with test generator
 ensure DUV outputs occur when expected
 ensure DUV outputs are correct
 ensure no spurious outputs occur
Verilog
Example: Multiplier Testbench

`timescale 1ns/1ns
module multiplier_testbench;
parameter t_c = 50;
reg clk, reset;
reg input_rdy;
wire signed [3:-12] a_r, a_i, b_r, b_i;
wire signed [7:-24] p_r, p_i;
real real_a_r, real_a_i, real_b_r, real_b_i,
real_p_r, real_p_i, err_p_r, err_p_i;
task apply_test ( input real a_r_test, a_i_test,

b_r_test, b_i_test );
begin
real_a_r = a_r_test; real_a_i = a_i_test;
real_b_r = b_r_test; real_b_i = b_i_test;
input_rdy = 1'b1;
@(negedge clk) input_rdy = 1'b0;
repeat (5) @(negedge clk);
end
endtask

Verilog

multiplier duv ( .clk(clk), .reset(reset),
.input_rdy(input_rdy),
.a_r(a_r), .a_i(a_i),
.b_r(b_r), .b_i(b_i),
.p_r(p_r), .p_i(p_i) );
always begin // Clock generator
#(t_c/2) clk = 1'b1;
#(t_c/2) clk = 1'b0;
end
initial begin // Reset generator
reset <= 1'b1;
#(2*t_c) reset = 1'b0;
end

Verilog

initial begin // Apply test cases
@(negedge reset)
@(negedge clk)
apply_test(0.0, 0.0, 1.0, 2.0);
apply_test(1.0, 1.0, 1.0, 1.0);
// further test cases ...
$finish;
end
assign a_r = $rtoi(real_a_r * 2**12);
assign a_i = $rtoi(real_a_i * 2**12);
assign b_r = $rtoi(real_b_r * 2**12);
assign b_i = $rtoi(real_b_i * 2**12);

Verilog

always @(posedge clk) // Check outputs
if (input_rdy) begin
real_p_r = real_a_r * real_b_r - real_a_i * real_b_i;
real_p_i = real_a_r * real_b_i + real_a_i * real_b_r;
repeat (5) @(negedge clk);
err_p_r = $itor(p_r)/2**(-24) - real_p_r;
err_p_i = $itor(p_i)/2**(-24) - real_p_i;
if (!( -(2.0**(-12)) < err_p_r && err_p_r < 2.0**(-12) &&
-(2.0**(-12)) < err_p_i && err_p_i < 2.0**(-12) ))
$display("Result precision requirement not met");
end
endmodule

Verilog
Asynchronous Timing
 Clocked synchronous timing requires
 global clock distribution with minimal skew
 path delay between registers < clock period
 Hard to achieve in complex multi-GHz systems
 Globally asynch, local synch (GALS) systems
 Divide the systems into local clock domains
 Inter-domain signals treated as asynch inputs
 Simplifies clock managements and constraints
 Delays inter-domain communication
 Delay-insensitive asynchronous systems
 no clock signals

Verilog
Other Clock-Related Issues

 Inter-chip clocking
 Distributing high-speed clocks on PCBs is hard
 Often use slower off-chip clock, with on-chip clock
a multiple of off-chip clock
 Synchronize on-chip with phase-locked loop (PLL)
 In multi-PCB systems
 treat off-PCB signals as asynch inputs
 Low power design
 Continuous clocking wastes power
 Clock gating: turn off clock to idle subsystems

Verilog
Summary
 Registers for storing data
 synchronous and asynchronous control
 clock enable, reset, preset
 Latches: level-sensitive
 usually unintentional in Verilog
 Counters
 free-running dividers, terminal count,
reset, load, up/down

Verilog
Summary
 RTL organization of digital systems
 datapath and control section
 Finite-State Machine (FSM)
 states, inputs, transition/output functions
 Moore and Mealy FSMs
 bubble diagrams
 Clocked synch timing and constraints
 critical path and optimization
 Asynch inputs, switch debouncing
 Verification of sequential systems

Digital Design: An Embedded Systems Approach Using Verilog: Sequential Basics

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Digital Design: An Embedded Systems Approach Using Verilog: Sequential Basics

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Digital Design:

Digital Design — Chapter 4 — Sequential Basics 2

 Other kinds of flipflops

Digital Design — Chapter 4 — Sequential Basics 3

Pipelines Using Registers

combin- combin- combin-

combin- combin- combin-

Clock period = max(Delay1, Delay2, Delay3)

module average_pipeline ( output reg signed [5:-8] avg,

wire signed [5:-8] a_plus_b, sum, sum_div_3;

Digital Design — Chapter 4 — Sequential Basics 6

Digital Design — Chapter 4 — Sequential Basics 7

D-Flipflop with Enable

 CE is a synchronous control input

Register with Enable

always @(posedge clk)

Digital Design — Chapter 4 — Sequential Basics 9

Register with Synchronous Reset

always @(posedge clk)

Register with Asynchronous Reset

Digital Design — Chapter 4 — Sequential Basics 11

Asynch Reset in Verilog

always @(posedge clk or posedge reset)

 reset is an asynchronous control input here

Digital Design — Chapter 4 — Sequential Basics 12

Flipflop and Register Variations

module flip_flop_n ( output reg Q,

p re always @( negedge clk_n or

Digital Design — Chapter 4 — Sequential Basics 14

Digital Design — Chapter 4 — Sequential Basics 15

Example: Sequential Multiplier

Digital Design — Chapter 4 — Sequential Basics 16

Digital Design — Chapter 4 — Sequential Basics 17

 Current RTL synthesis tools don’t accept

 Values must be stored

Digital Design — Chapter 4 — Sequential Basics 20

 Increments every rising edge of clk

Digital Design — Chapter 4 — Sequential Basics 21

Example: Periodic Control Signal

Digital Design — Chapter 4 — Sequential Basics 22

Example: Periodic Control Signal

module decoded_counter ( output ctrl,

Digital Design — Chapter 4 — Sequential Basics 23

Count Enable and Reset

 Increments when CE = 1 on rising clock

 TC is 1 for one cycle in every 2n cycles

Digital Design — Chapter 4 — Sequential Basics 26

Digital Design — Chapter 4 — Sequential Basics 27

Decade Counter in Verilog

module decade_counter ( output reg [3:0] q,

Digital Design — Chapter 4 — Sequential Basics 28

Down Counter with Load

Digital Design — Chapter 4 — Sequential Basics 29

Loadable Counter in Verilog

module interval_timer_rtl ( output tc,

Digital Design — Chapter 4 — Sequential Basics 30

Reloading Counter in Verilog

Digital Design — Chapter 4 — Sequential Basics 31

Digital Design — Chapter 4 — Sequential Basics 32

Ripple or Synch Counter?

Digital Design — Chapter 4 — Sequential Basics 33

Datapaths and Control

Example: Complex Multiplier