Module 1 : Chapter 1

BASIC STRUCTURE OF
COMPUTERS

Ms. Yashaswini Jogi

CSE Dept.
SMVITM
1.1 Basic
Operational
Concepts
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Review
 Activity in a computer is governed by instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
 Individual instructions are brought from the
memory into the processor, which executes the
specified operations.
 Data to be used as operands are also stored in the
memory.
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 An Instruction consists of two parts, an Operation

code and operand/s as shown below:

ADD LOCA, R0

OPERANDS
OPCODES
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 Let us see a typical instruction

ADD LOCA, R0
 This instruction is an addition operation.

The following are the steps to execute the instruction:

 Step 1: Fetch the instruction from main memory into the
processor
 Step 2: Fetch the operand at location LOCA from main
memory into the processor
 Step 3: Add the memory operand (i.e. fetched contents of
LOCA) to the contents of register R0
 Step 4: Store the result (sum) in R0.
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 The same instruction can be realized using two instructions

as
Load LOCA, R1
Add R1, R0
The steps to execute the instructions can be enumerated as
below:
 Step 1: Fetch the instruction from main memory into the
processor
 Step 2: Fetch the operand at location LOCA from main
memory into the processor Register R1
 Step 3: Add the content of Register R1 and the contents of
register R0
 Step 4: Store the result (sum) in R0.
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Figure 1.2 below shows how the memory and

the processor are connected.

Processor
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 The processor contains ALU, control-circuitry and many

registers.
Registers are
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)
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 The IR (Instruction Register) contains the instruction that is being executed.

Before the IR executes the instruction it needs to be decoded first. As soon as the
content of the MDR is transferred to the IR, the decoding process commences.
After decoding, execution of the instruction will take place.
 The PC (Program Counter) contains the memory address of the instruction to be
executed. During execution, the contents of the PC are updated to point to the
next instruction. Every time that an instruction is to be executed, the program
counter releases its contents to the internal bus and sends it to the memory
address register.
 The MAR (Memory Address Register) holds the address of the location to or
from which data are to be transferred. As can be seen from the figure above, the
connection of the MAR to the main memory is one-way or unidirectional.
 The MDR (Memory Data Register) contains the data to be written or read out of
the addressed location.
 During the fetch operation, the MDR contains the instruction to be executed or
data needed during execution. In write operation, MDR the data to be written
into the main memory.
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Typical Operating Steps

 1. PC is set to point to the first instruction of the program (the
operating system loads the memory address of the first instruction).
 2. The contents of the PC are transferred to the MAR (which is
automatically transmitted to the MM) and a Read signal is sent to the
MM.
 3. The addressed word is read out of MM and loaded into the MDR.
 4. The contents of MDR are transferred to the IR. The instruction is
ready to be decoded and executed.
 5. During execution, the contents of the PC are incremented or updated
to point to the next instruction.
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summary
1. [MAR] <= [PC]
2. [MDR] <= [[MAR]]
3. [IR] <= [MDR]
4. [PC] <= [PC] + 4
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CPU Instruction Execution Steps

Instruction execution in a CPU can now be summarized by the following
steps:
1. Fetching the instruction from the memory into the instruction register.
2. Incrementing the PC to point to the next instruction to be executed.
3. Determining the type of instruction fetched (instruction decoding).
4. Determining the location of data in the memory. If the instruction uses
data.
5. Fetching the required data into internal CPU registers.
6. Executing the instruction.
7. Storing the results in the designated locations.
8. Return to Step 1.
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Home Work 1
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Home Work 2
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Interrupt

 Normal execution of programs may be preempted if some device

requires urgent servicing.
 The normal execution of the current program must be interrupted –
the device raises an interrupt signal.
 Interrupt-service routine
 Current system information backup and restore (PC, general-purpose
registers, control information, specific information)
1.2 Bus
Structures
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Bus Structures
 There are many ways to connect different
parts inside a computer together.
 A group of lines that serves as a connecting
path for several devices is called a bus.
 Address/data/control
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Bus Structure
 Single-bus

Input Output Memory Processor

Figure 1.3. Single-bus structure.

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Speed Issue
 Different devices have different
transfer/operate speed.
 If the speed of bus is bounded by the
slowest device connected to it, the
efficiency will be very low.
 How to solve this?
 A common approach – use buffers.
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Thank you