Computer Interfacing

Lecture 3
 Outside environment (analog/ digital inputs )

Digital input

Analog input
Standard input
port Interface card A/D converter

Standard bus

Processor

Standard bus

Standard output Interface card

port D/A converter

Outside environment
Computer buses
Definition:
• In computer architecture, a bus is a
communication system that transfers data
between components inside a computer, or
between computers.

• A bus is a collection of wires and connectors

that connect any device with the processor. 
1.Micro channel architecture MCA
• MCA is parallel local
bus created at 1987
• Created by IBM.
• Data bus= 32 or 16.
• Address bus = 32.
• Clock rate 10 MHz
2.Extended Industry Standard Architecture

• Extended Industry Standard

Architecture (EISA) parallel
local bus released by 1988.
• Completely compatible
with the ISA bus
• EISA has a 32 address
lines.
• EISA has a 32 data lines.
• Clock rate = 33 MHz.
3.VESA local Bus
• 1990s the I/O bandwidth of the ISA bus becomes a
bottleneck to PC graphics performance.

• VESA created by 1992.

• VESA worked alongside the ISA bus.

• VESA concerns with memory-mapped I/O and DMA,

while ISA bus handled interrupts and port mapped I/O.
4.Peripheral Component Interconnect PCI
bus
• PCI released 1992.
• Clock rate up to 66MHz.
• PCI bus has 124 line divided on two groups A
and B.
• Typical IBM motherboard includes 3-4 PCI
slots
4.Peripheral Component Interconnect PCI
bus

Advantage:
Unlike ISA more than one device could share
the same IRQ without any interference.
4.Peripheral Component Interconnect PCI
bus

Typical 32-bit PCI card

4.Peripheral Component Interconnect PCI
bus
4.Peripheral Component Interconnect bus
PCI

Typical 32-bit PCI bus lines

4.Peripheral Component Interconnect PCI
bus

• AD(x): address/ data lines.

– Using time multiplexing on the same lines- address signals first
then the data signals.
– Multiplexing of address and data bus reducing the number of pins

• Clk signal

• Frame: indicate whether address phase or data phase .

• DEVSEL: Device select.

4.Peripheral Component Interconnect PCI
bus

• INT(x): Interrupt lines.

• SERR: system error.

• RST: Reset.

• GNT: bus grand from motherboard to card.

• REQ: bus request from card to motherboard.

4.Peripheral Component Interconnect PCI
bus
Bus mastering:
–  Bus mastering is a feature supported by many bus architectures that enables a device connected to
the bus to initiate transactions.

– It is also referred to as "first-party DMA", in contrast with "third-party DMA" where a system DMA
controller (also known as peripheral processor, I/O processor, or channel) actually does the transfer.

– PCI, allows multiple devices to bus master .

– Thus, there needs for a bus arbitration scheme to prevent multiple devices attempting to drive the
bus simultaneously.

– A number of different schemes are used. PCI does not specify the algorithm to use, leaving it up to
the implementation to set priorities.
4.Peripheral Component Interconnect PCI
bus
Bus mastering:

– PCI uses the REQ, GNT signals.

– PCI bus master activates the REQ signal to indicate
a request to the PCI bus.
– Arbitration unit then activates GNT signals so that
the requesting master gains control of the bus.
4.Peripheral Component Interconnect PCI
bus
PCI bus transactions

 PCI bus traffic consists of a series of PCI bus transactions.

 Each transaction consists of an address phase followed by one

or more data phases.

 The direction of the data phases may be either write transaction

or read transaction.

 All data phases must be in the same direction.

4.Peripheral Component Interconnect PCI
bus
PCI bus transactions
 Any device may initiate a transaction by requesting permission from the
bus arbitration unit.

 The arbitration unit grants permission to one of the requesting devices.

 The initiator begins the address phase by broadcasting a 32- bit address
plus a 4 bit command code, then waits for a target to respond.

 All other devices examine this address and one of them responds.
4.Peripheral Component Interconnect PCI
bus
PCI command codes:
C/BE0 -C/BE3 : signals are to indicate data
transaction type during the address phase of this
transaction.

PCI targets must examine the command code as well

as the address and not to respond to address phases
which specify an unsupported command code.
4.Peripheral Component Interconnect PCI
bus
PCI command codes:
4.Peripheral Component Interconnect PCI
bus
PCI command codes:

– INTA sequence: interrupt acknowledge.

– Special cycle: used to transfer information to the PCI device about the processor
status.

– I/O read access: indicates a read operation for I/O address memory.

– I/O write access: indicates a write operation to an I/O address memory

– Memory read access direct memory read operation

– Memory write access direct memory write operation