EEDG/CE/CS 6304 Computer Architecture

Lecture 14 – Buses

Benjamin Carrion Schaefer

Associate Professor
Department of Electrical and Computer Engineering
Course Overview
• Fundamentals of Design and Analysis of
Computers (2 lectures)
– History, technological breakthroughs, etc.
– Trends and metrics: performance,
power/energy, cost
• CPU (7 Lectures)
– Instruction Set Architecture
– Arithmetic for Computers (new)
– Instruction Level Parallelism (ILP)
– Dynamic instruction scheduling
– Branch prediction
– Thread-level parallelism
– Modern processors
• Memories (4 Lectures)
– Memory hierarchy
– Caches
– Secondary storage
– Virtual memory
• Buses (1 lecture)
• New computer structures: Heterogeneous
computing (1 lecture)
Learning Objectives
Upon completion of this chapter, you will be able to:
– Describe the evolution of bus architecture from
ISA to PCI and USB
– Define the meaning of the terms masters, slave,
bus arbitration, bus protocol, and bus bandwidth
and describe their importance in PC design
– List the major characteristics of the PCI and PCIe
buses
– List the major characteristics of the USB bus
– Contrast and compare the performance of ISA,
PCI, and USB buses

Ref: The x86 PC, 5th Edition, M. Ali Mazidi, J. G. Mazidi and D. Causey, Ed.
Pearson – Chapter 26 and 27
Ref: Miscellaneous sources 3
Buses
• Bus is a communication system that transfers
data between components (from Latin
"omnibus", meaning "for all")

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Simplified Illustration of a Bus
Buses
• Set of lines to which several devices may be connected
• Enables data to be transferred from one device to any other
• Logic gate that sends data over a bus line is called the bus driver
• All devices connected to the bus can send data, but only 1 can drive the
data at a time → tri-state gates (if control signal is high output is Z)
• E.g., of how to connected a 1-bit device to a bus:

Rin Bus Q D Qnew Operation

0 X 0 0 0 Feed Q back
0 X 1 1 1 Feed Q back

1 0 X 0 0 Read data from bus

1 1 X 1 1 Read data from bus

Rin = 0 : feeds back Q Rout = 0 : Output is ‘Z’ decouples FF from bus

Rin = 1: select the data on the bus Rout = 1: Writes Q to the bus
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Simple Bus Architecture
• Simplified motherboard of a personal computer
Internal Computer Organization
• Pentium Based
Computers
– CPU
– Memory
– Video (AGP)
– Northbridge
(fast
interconnect)
• FSB : Front
Side Bus
• AGP :
Accelerated
Graphics
Port
– Southbridge
(slow
peripherals)
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Don’t….

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Motherboard Overview
• PCB that interconnects all PC components
Memory
slots Chipset

PCI bus Processor

slots socket

ISA bus
slots

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 AGP: Advanced
Graphics Port

PCI: Peripheral Component Interconnect

IDE: Integrated
Drive Electronics

SCSI: Small Computer

System Interface
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Buses Overview - ISA
• PC bus supports 8 data bits and provides 62-pin I/O
channel slots
• ISA (Industry Standard Architecture) bus supports 16
data bits and provides several 62-pin I/O channel slot
+ 36-pin auxiliary slot

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Buses Overview – EISA - PCI
• EISA (Extended Industry Standard Architecture) bus
supports 32 data bits and provides 157 bus lines
and 186-pin slots
Downward compatibility: functionality and plug
compatibility (EISA → ISA → PC Bus)
• PCI (Peripheral Component Interconnect) local bus:
an advanced high-performance local bus that
supports multiple peripheral devices.
EISA Slots

PCI bus
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Computer Architecture and Bus Evolution

ISA bus

IBM PC 5150 PCI+AGP 14

Units
• Bandwidth units = Amount of data/ unit of time
• Question: Kilo = 1,000 or 1,024 (210)?

Wikipedia
Bandwidth of Different Buses

M = 106

16.6 132 If 1 mega = 106

Bandwidth (megabytes/s) 7.63 15.84 62.94 126.84 If 1 mega = 220 =

1,048,576

PCI bandwidth(1mega = 106) =(32/8 * 33 *1,000,000/1,000,000)/2 = 66

PCI bandwidth (1 mega = 220) =(32/8 * 33 *1,000,000/1,048,576)/2 = 62.94

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ISA BUS

• In PCs with x86 microprocessors, signals for the ISA

expansion slots are provided by the chipset.
– The chipset makes sure signals for the ISA slot
conform with the ISA bus standard regardless of
CPU speed and data width.
• ISA bus specifications and timing for memory are
precise and must be understood to design an ISA plug-
in card with on-board memory.

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ISA BUS –Bus Slot Signals
Address and Data Lines:
SA0–SA19 (system address)
Provides address signals
for the desired memory
or I/O location.
The chipset latches these signals &
holds them valid throughout the
bus cycle.
SD0–SD15 (system data bus)
Transfers data between
CPU, memory & I/O devices.

62 pins
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ISA BUS – Component Side
LA17–LA23 (latchable address)
With SA0–SA19, gives access to
16M of memory space from the
ISA slot.
These signals are latched
by the board designed for
the expansion slot.
SD0–SD15 (system data bus)
Transfers data between
CPU, memory & I/O devices.

36 pins

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PCI BUS
• PCI was conceived as a specification standard for peripheral
connections for Intel's high-performance microprocessors such
as the 80486 and Pentium.
– Intel developed PCI local bus specifications, available free of
charge to all PC & add-in board manufacturers
• A local bus standard with the pin-out for expansion slot
connections, PCI incorporates these features:
– Burst mode data transfer; Level-triggered interrupts.
– Bus mastering; Automatic configuration; High bandwidth.
– A bridge which allows any kind of add-in card based
on ISA to be plugged into the PCI local bus.

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Peripheral Component Interconnect (PCI) Bus
Characteristics
• More important PCI characteristics:
– PCI supports both 5- and 3.3-V expansion cards.
• Cutouts (keys) prevents users from plugging a card with
one voltage into a motherboard with a different voltage
– It provides auto-configuration capability
• A user can install a new add-in card without setting
DIP switches, jumpers, and selecting the interrupt.
• Level-triggered interrupts support interrupt sharing.
– It supports up to 10 peripherals
– Use of a highly refined connector with a small area of
contact makes the PCI bus a high-frequency bus.

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PCI Bus
• PCI (Peripheral Component Interconnect) Local high-
performance bus:
– 32-bit or 64-bit bus with multiplexed address and data lines @ 33 or 66
MHZ
• Interconnect mechanism between:
– peripheral controller components
– add-in boards
– processor
PCI BUS – Master-Slave
• Many devices connected together communicate with each
other via address, data & control buses.
– When one device wishes to communicate with another,
it sends an address to distinguish it from others
– It also sends a read or write signal to indicate its intention
• A master device initiates & controls communication.
– The responding device is called the slave.
• In x86-based PCs, the CPU is an example of a master and
memory is an example of a slave.

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PCI – Bus Arbitration

• There is only one set of global address, data, and control

buses available in a given system.
– To access the buses, a master must ask permission of the
central bus arbitrator & and wait for a response.
– Requests by more than one master to use the buses must
be arbitrated in an orderly fashion:
1. Fixed arbitration (daisy chain)
2. Centralized arbitration (e.g., Round robin. Priority changes in
fixed patterns)
3. Dynamic priority change (priority changes in a non-fixed pattern)

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Fixed Arbitration – Daisy Chain
• Chain of serially connected components
• Priority of an interface is determined by its
position in the chain.

Daisy chain : Garland of Daisy flowers

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Fixed Arbitration – Daisy Chain
Device 1 Device 2 Device N
Highest Lowest
Priority Priority

Ack Ack Ack

Bus Release
Arbiter Request

wired-OR
Data/Addr

• Advantage: simple
• Disadvantages:
– Cannot assure fairness – a low-priority device may be
locked out indefinitely
– Slower – the daisy chain grant signal limits the bus speed
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Daisy-chained Interrupt Example

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Example of Fixed Arbitration

• SCSI Protocol
– Each device has a SCSI ID used to identify it on the bus
– When multiple devices request the bus → the one
with highest ID wins and is allowed to access the bus
• Advantage:
– Easy to decided which devices gets access to the bus
• Disadvantage:
– Can prevent a device with a lower ID from ever getting
a chance to access the bus → starvation
Example: SCSI
• A SCSI bus has four devices attached to it. With IDs 1,
2, 3, and 4. If each device wants to use 30 MB/s of bus
bandwidth, and the total bandwidth of the SCSI bus is
80 MB/s, how much bandwidth will each device be
able to use?
Example: SCSI Solution
• A SCSI bus has four devices attached to it. With IDs 1,
2, 3, and 4. If each device wants to use 30 MB/s of bus
bandwidth, and the total bandwidth of the SCSI bus is
80 MB/s, how much bandwidth will each device be
able to use?

Solution:
• Device 4 has the highest priority, so it gets access to the bus whenever it tries
and is able to use its full 30 MB/s.
• Of the 50 MB/s remaining, device 3 is able to use 30 MB/s, because it only
loses arbitration when device 4 wants to use the bus.
• Device 2 uses all of the remaining 20 MB/s, because it always beats device 1,
which gets no bandwidth (here we are ignoring start up issues –device 1 might
get one chance to access the bus if its first request was made before any of the
other devices wanted to use the bus.
Centralized Parallel Arbitration
Device 1 Device 2 Device N

Request1 Request2 RequestN

Ack1
Ack2
Bus
Arbiter AckN

Data/Addr

• Advantages: flexible, can assure fairness

• Disadvantages: more complicated arbiter hardware
• Used in essentially all processor-memory buses and in
high-speed I/O buses

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Bus Protocol
• To coordinate activity, buses follow a strict set of timing and signal
specifications, called bus protocol.
– Synchronous protocol - bus activity is synchronized according to a
central frequency—the timing of the central clock oscillator (e.g.,
interface with memory which has strict timing constraints)
– Asynchronous protocol - decides when it is ready and does not
operate according to the central clock frequency (e.g., x86 printer
interfacing)
• Asynchronous is used when there is a mismatch between the bus timing
of the master and slave.
• Synchronous protocol generally has a higher rate of data transfer than
asynchronous protocol.

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PCI BUS Video Requirements

where 1 M = 220

Bandwidth (1024x768) = 1024 x 768 x 16/8 * 10 * 106 /220 ~ 15Mbytes/s

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PCI BUS Video Requirements con’t

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PCI BUS Video Requirements con’t - Solution

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PCI Local Bus Characteristics
• Important characteristics of the PCI local bus:
– Maximum speed of 33 MHz (extended to 66 MHz)
– 32- & 64-bit data paths.
– Burst mode data transfer of 2-1-1-1 used by microprocessors such as
the Pentium.
– Bus mastering, for multiprocessor implementation, where any number
of microprocessors can become master and take control of the buses.
– With implementation of a bus bridge, it supports the slow ISA bus.
• Buffers in the bridge allow the processor to write into the buffer,
leaving the task of handling ISA to the bridge.

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PCI Performance
• The PCI local bus supports both single memory cycle and burst mode.
– Single cycle takes 2 clocks to read or write a word of data.
– In the first clock, the address is provided and in each subsequent clock, the
data is accessed.
• This makes it 2-1-1-1-1-1....

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PCI Performance - Solution
• The PCI local bus supports both single memory cycle and burst mode.
– Single cycle takes 2 clocks to read or write a word of data.
– In the first clock, the address is provided and in each subsequent clock, the
data is accessed.
• This makes it 2-1-1-1-1-1....

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PCI Performance

where
1 M = 106
1 K = 103

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PCI Express (PCIe)
• Supersedes PCI and AGP
• High-speed serial computer expansion bus standard
• PCIe has numerous improvements over the
aforementioned bus standards, including:
– higher maximum system bus throughput
– lower I/O pin count
– smaller physical footprint
– better performance-scaling for bus devices
– a more detailed error detection and reporting mechanism
(Advanced Error Reporting (AER))
– native hot-plug functionality.

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PCIe Types

• Physical PCIe slots may

contain from one to
thirty-two lanes

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PCIe Topology

• Switch instead of arbiter

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PCIe Topology con’t
• Single Hub as Chipset (ICH-Intel Communications
Chipset/Hub)

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PCI vs. PCIe
PCI
Parallel Bus architecture
All devices share a common set of
address/data/control lines
Arbiter needed and only one
master at a time has control
Bus clock speed limited to slowest
peripheral on the bus
PCIe
Serial bus
Based on point-to-point topology
with separate serial links
No arbiter needed. Multiple
connections at a time
Point-to point full-duplex with no
inherent limitation
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Universal Serial Bus (USB)
The Easy Way to Plug & Play. Anything. Anytime. Anyone.

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USB
• Originally developed in 1995 by a consortium including
– Compaq, HP, Intel, Lucent, Microsoft, and Philips
• USB 1.1 supports (1996)
– Low-speed devices (1.5 Mbps)
– Full-speed devices (12 Mbps)
• USB 2.0 supports (2000)
– High-speed devices
• Up to 480 Mbps (a factor of 40 over USB 1.1)
– Uses the same connectors
• Transmission speed is negotiated on device-by-device basis
– USB 3.0 (2008)
• Superspeed = 6 Gbit/s
• USB 3.2 up to 20 Gbit/s
USB (cont’d)
• Motivation for USB
– Avoid device-specific interfaces
• Eliminates multitude of interfaces
– PS/2, serial, parallel, monitor, microphone, keyboard,…
– Avoid non-shareable interfaces
• Standard interfaces support only one device
– Avoid I/O address space and IRQ problems
• USB does not require memory or address space
– Avoid installation and configuration problems
• Don’t have to open the box to install and configure jumpers
– Allow hot attachment of devices
USB (cont’d)
• Additional advantages of USB
– Power distribution
• Simple devices can be bus-powered
– Examples: mouse, keyboards, floppy disk drives, wireless LANs,
coffee warmers, reading lights, MP3 players, …
– Control peripherals
• Possible because USB allows data to flow in both
directions
– Expandable through hubs
– Power conservation
• Enters suspend state if there is no activity for 3 ms
– Error detection and recovery
• Uses CRC
USB Ports - Bus Comparison
• A comparison of ISA, PCI, COM, LPT, and USB.
– In the calculation of data transfer rate (bus bandwidth) for ISA & PCI
buses, a 2-clock read/write cycle is assumed.
– 2-microsecond timing for the parallel port is assumed.

Microsoft & Intel have

worked to eliminate ISA
bus, LPT, & COM ports
from PC motherboards.
Today’s desktop PCs have
PCIe & USB ports only.

USB 3.0 1 6.0 G bits/second

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Standard socket, but different Hub

• USB 3.0 and USB 2.0 socket example

Host, Peripherals and Hubs (cont.)
• In boards with two or more USB ports, the hub is incorporated into the host—
on the x86 board it is commonly referred to as the root hub.

The root hub on an x86 motherboard

has from two to six ports.

Each port can be connected to a

peripheral I/O device or another hub.

To attach more peripheral I/O devices, an

external hub is used to expand the
number of USB ports.

Figure 27-1 Host and Root Hub in x86 PC

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USB Host Peripheral Controller
• Cypress IC
– Single chip programmable USB dual-role (Host/Peripheral)controller
with two configurable Serial Interface Engines (SIEs)and four USB
ports
– 8K x 16 internal RAM for code and data buffering

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Host, Peripherals and Hubs
• There are two types of external hubs:
– Bus-powered - power source comes from the root hub
of the host PC via a USB cable.
– Self-powered - the hub has its own power source.
• It is also referred to as an externally powered hub.

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Host, Peripherals and Hubs (cont.)
• A majority of peripheral devices in everyday use,
are bus-powered, such as Flash memory sticks.
– USB provides power.
• USB electrical current allocated in units of 100mA
up to a maximum of 500mA per port
– The host can provide a maximum of 500 mA of
current (5V power source) per A-connector
– The hub uses 100 mA
– As each downstream peripheral port must
be given up to 500 mA, the number of downstream
peripheral ports in the bus-powered hub is
limited to 4.
• 4 x 100 mA + 100 mA = 500mA

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Host, Peripherals and Hubs (cont.)
• The self-powered external hub takes power from a source other than the
motherboard.
– Generally from the wall outlet.

Printers with USB ports often have self-

powered hubs, drawing from the printer
power supply.

Devices with I/O functions and hub

are often called compound devices.

Figure 27-3 Bus-Powered and Self-Powered Hubs

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Daisy chaining the Hubs

• The USB bus allows up to five levels of external

hubs to be connected to the root hub.
– Due to power considerations, many of these
hubs must be self-powered.

– USB terminology uses the word tier instead

of level.

– The host (root hub) is counted

as the first tier (level).
– The number of external hubs that can be
cascaded together is limited to five.
– It states the total number of tiers (levels)
cannot be more than seven.
Figure 27-4 Daisy-Chaining Hubs

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USB Cable Signals
• The USB cable has four wires inside it:
– Vcc, Gnd for the power source
– D+, and D– for the data path

At any given time, data…

B
is going from the device A
to the host…
or is coming from the host
to the device…

but never at the same

Figure 27-2
time. USB Connectors

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USB cable signals (cont.)

• The USB cable does not have any wire for

clock to synchronize data transfer—it is an
asynchronous bus.
– The port uses the D+ and D– pins to implement
the asynchronous method of data transfer.
• It uses NRZI (none return to zero inverted) encoding.
– Maximum cable length for the USB is 5 meters (15
feet).
• Less than 5 meters for high-speed data transfers

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USB Lines/Pins
USB Electrical Specifications

Data bit D+ D-
1 high low

0 low high

• USB 2.0 Data path between host & peripheral is half-duplex

• USB 3.0 Full-duplex
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USB connectors

• Plethora of connectors

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USB C (2016)
• Defines a new reversible
plug connector
• 24-pin double-sided
connector
– Four PWR/GND
– Two differential pairs
for USB 2.0
– Four pairs for USB 3.0
– Config pin to detect
orientation
– Misc pins
• Support power current
up to 1.5A and 3.0A
• Used as only connector
to transfer data and
power the MacBook

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USB Video
Summary
• PC bus architectures
• PC motherboard
• Bandwidth calculations
• PC buses
– ISA, EISA, PCI, PCIe
– USB

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