VLSI Design Methodology

Customer Specifications

LOGIC DESIGN Logical

Library
VLSI Design Methodology
Customer Specifications

LOGIC DESIGN Logical

Library

PHYSICAL DESIGN
Physical
Library
VLSI Design Methodology
Customer Specifications

LOGIC DESIGN Logical

Library

PHYSICAL DESIGN
Physical
Library

FOUNDRY
VLSI Design Methodology
Customer Specifications

LOGIC DESIGN Logical

Library

PHYSICAL DESIGN
Physical
Library

FOUNDRY

ASIC
VLSI Design Methodology - simulation
Customer Specifications

Simulation
LOGIC DESIGN

PHYSICAL DESIGN

FOUNDRY

ASIC
Logic Design

A S

System

B C

S=A+ B

C = A.B
Logic Design

A A S
S=A+ B S
B = A‾.B + A.B‾
System

A C = A.B
B C C
B
Gate Level Schematic

A
+ S
B

C
Gate Level representation

C
Customer Specification : HA
Design

A
S
B

C
Requirement Specification

Test- Vectors
S=A+ B A B Carry Sum
C=A. B
Customer Specification : HA Schematic – gate level
Test -Bench
Design
A
S
B

C
Requirement Specification

Test –Bench
S=A+ B A B Carry Sum
- Results
C=A. B
0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0
Design Entry thru Schematic

Schematic Editor
P& R Schematic Entry Lib.

IO
Cells

P&G

Place

Route

Simul.
Design Entry - Schematic Editor

Schematic Editor
P& R Schematic Design Entry Lib.

IO
Cells
Design
P&G

Place

Route

Simul.
Verification - Test Bench

Schematic Editor
P& R Schematic Simulation Lib.

IO Test Bench
Cells
Design
P&G

Place

Route

Simul.
Logical Expression
S = A + B :C = A.B

A B S C Remarks

0 0 0 0

0 1 1 0

1 0 1 0
Verification – ha Design – Functional verification
0 5 10 15 20 25 30 35 40 time

Sum

Cout
Simulation - Design Entry using HDL

a Sum

half_Adder
b

Cout

module half_adder (a,b,sum,cout);

//port list does not differentiate
inputs and outputs
Simulation – ha Design

a Sum

Half_Adder

b
Cout

//do show now

input a,b;
output sum,cout;
Simulation – ha Design
Sum
a
XOR

Half_Adder

AND
b
Cout

//do show Logical Operation now

input a,b;
output sum,cout;
sum = a ^ b;
and (cout, a, b);
Simulation – ha Design – Behavioral model
module half_adder (a,b,sum,cout);
//port list does not differentiate inputs and
outputs
//do so now
input a,b;
output sum,cout;
//concurrent signal assignment on sum
//uses a dataflow expression assign
sum = a ^ b;
//AND primitive is used here
//implies structure
and (cout, a, b);
endmodule
Simulation – ha Design –waveform Viewing

//Observe
initial
begin $monitor($time, " : A = %b B = %b
Sum = %b Carry=%b", a,b,sum,cout);
end
endmodule
Simulation – ha design Verification

Test Bench
( HDL Code)

A Sum

Design
(HDL CODE)

B Cout

A & B – Test vectors generated by test bench Sum & Cout - Outputs
Simulation – ha Test Bench Design
• `include "half_adder.v“
• module stimulus;
• reg a,b;
• wire sum, cout;
• //Instantiate half_adder
• ha1(a,b,sum,cout);
• //Generate stimulus
• initial
• begin a = 1'b0; b = 1'b0;
• #5 a = 1'b0; b = 1'b1;
• #5 a = 1'b1; b = 1'b0;
• #5 a = 1'b1; b = 1'b1;
• end
• //Observe initial
• begin $monitor($time, " : A = %b B = %b Sum = %b Carry =
• %b",a,b,sum,cout);
• end
• endmodule
Simulation – ha Design – Functional verification
0 5 10 15 20 25 30 35 40 time

Sum

Cout
VLSI Design methodology - Synthesis
Customer Specifications

Simulation Big free RTL Code

LOGIC DESIGN
Synthesis

ASIC
Synthesis

Bug free HDL Code

LOGIC SYNTHESIS
1.Translation
2.Optimization
3. Mapping

Gate Level Netlist

Synthesis – appending Logic Library
Customer Specifications

Simulation
LOGIC DESIGN
Synthesis Logical
Gate Level netlist
Library

ASIC
Synthesis – Logic & Physical Libraries
Component
Type Physical Library
Logic Library
BUFFER

INVERTER

AND
d d

OR d

Flip- Flop
Synthesis – I.Translation

Tool Specific
Translation Generic code
HDL Code (like Algorithm)

sum = a ^ b;
and (cout, a, b);
Synthesis – 2.Optimization
A_ A A_ A

B_ B_
0 1 0 0

B B
1 0 0 1

Sum = ( A_ . B + A . B_ ) Cout = ( A . B )
Synthesis – 3.Mapping

Optimized Generic Code Technology Library

- Logic gates
L,2L ,4L ,XL Types
Sum = ( A_ . B + A . B_ ) Mapping of * - Buffers
Generic code * - Inverters
* - NAND
Cout = ( A . B ) To * - NOR
Technology * - AOI
Components * - OAI
* - Latches
* - Flip-Flops
***
***
* - IO Cells
* - Macros
***
***
Schematic diagram after Synthesis

U3/AND L

A Sum
AND
U5/ or XL
U1/Inv L

U2/Inv L U4/AND L

Cout
AND
B
U6/AND 2L

AND
Synthesis-gate level netlist-structural model
• Module ha sum, cout, A, B ;
• Output sum, cout ;
• Input A, B ;
• not L u1 B_ B ;
• not L u2 A_ A ;
• and L u3 X a b_ ;
• And L u4 Y b a_ ;
• Or XL u5 sum X y ;
• And 2L u6 Cout a b ;
• endmodule
Physical Design – floor planning
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN

ASIC
Physical Design – floor planning
Cell Boundary

VDD

U1 U2 U3 U5 U6
U4
Not L Not L AND L Or XL AND 2L
AND L

VSS
Physical Design – place & route
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Library

ASIC
Physical Design – placement
Cell Boundary

VDD

U3 U5 U6
U4
AND L Or XL AND 2L
AND L

U1 U2
Not L Not L

VSS
 Physical Design – routing
Cell Boundary

VDD
U3 AND L U4 AND L U5 Or XL U6 AND 2L

A A B
A A
A X S
U2NotL X Y S
U1NotL C

BB A
A B Y B C
BB BB C

VSS
Physical Design – physical verification
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Physical verification Library

ASIC
 Physical Design – physical verification/DRC
Cell Boundary

VDD
U3 AND L U4 AND L U5 Or XL U6 AND 2L

A A B
A A
A X S
U2NotL X Y S
U1NotL C

BB A
A B Y B C
BB BB C

VSS
Physical Design – physical verification/LVS

Schematic netlist The Difference Layout Netlist

Should be Zero
VLSI Design Methodology – Mask Preparation
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Physical verification Library

Mask Preparation

FOUNDRY Die Fabrication

Package & Test

ASIC
Layer deposition using Mask
Source

Mask
Layer deposited
Substrate
 Pattern Creation Using Mask

Opaque

Transparent

Deposited Layer
Pattern using Set Of Masks
VLSI Design Methodology – die fabrication
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Physical verification Library

Mask Preparation

FOUNDRY Die Fabrication

Package & Test

ASIC
Foundry – Fabrication Process

MASKS
Processed Wafer
• Processing Equipment

• Jigs & Fixtures

Wafer
• Clean Rooms

• online Process Monitoring & test

DIE
Chemicals

ASIC Die Mount

On Package
Encapsulate
Wafer scribing to create Die
VLSI Design Methodology
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Physical verification Library

Mask Preparation

FOUNDRY Die Fabrication

Packaging & Test

ASIC
Die Bonding
Magnified View of a Die
IC Packages
ASIC
VLSI Design Methodology - Summary
Customer Specifications

Simulation
LOGIC DESIGN Logical
Synthesis Library

Floor Planning

PHYSICAL DESIGN Place & Route

Physical
Physical verification Library

Mask Preparation

FOUNDRY Die Fabrication

Package & Test

ASIC
Assignment :
Customer Specification : FA
Sum = (A + B) + C
A
B Sum

Carry = ab OR bc OR ac C
= ab OR (a XOR b)c

Carry