BASIC STA TERMINOLOGIES

VAIBHAV SONEWANE
POTP-FPGA
 1. SEED

• The Fitter seed affects the initial placement configuration of the design.
• Any change in the initial conditions changes the Fitter results; accordingly, each
seed value results in a somewhat different fit.
• It can have any integer value.
• If only a small number of paths are failing by small negative slack, then you can
try with a different seed to find a fit that meets constraints in the Fitter seed noise.
• It is impossible to try all seeds and get the absolute best result. running a seed
sweep (compiling your design with multiple seeds) determines whether the
average result improved after an optimization change or not.
 2. ROUTER TIMING OPTIMIZATION
LEVEL

• Values : NORMAL, MINIMUM, MAXIMUM

• Controls how aggressively the router tries to meet timing requirements.
• Setting this option to Maximum can increase design speed slightly, at the cost
of increased compile time.
• Setting this option to Minimum can reduce compile time, at the cost of slightly
reduced design speed.
• The default value is Normal.
 3. ROUTER EFFORT MULTIPLIER

• The Router Effort Multiplier controls how quickly the router tries to find a valid solution.
• The default value is 1(one) and legal values must be greater than 0(Any positive, non-zero
value).
• Numbers higher than 1 help designs that are difficult to route by increasing the routing effort.
• Numbers closer to 0 (for example, 0.1) can reduce router runtime, but usually reduce routing
quality slightly.
• Using a Router Effort Multiplier higher than the default value can benefit designs with
complex datapaths with more than five levels of logic. However, congestion in a design is
primarily due to placement, and increasing the Router Effort Multiplier does not necessarily
reduce congestion.
 4. PLACEMENT EFFORT MULTIPLIER

• Specifies the relative time the Fitter spends in placement.

• The default value is 1.0, and legal values must be greater than 0(Any positive,
non-zero value).
• Specifying a floating-point number allows you to control the placement effort.
• A higher value increases CPU time but may improve placement quality.
• For example, a value of '4' increases fitting time by approximately 2 to 4 times but
may increase quality.
• Numbers between 0 and 1 can reduce fitting time, but also can reduce placement
quality and design performance.
 5. FITTER EFFORT

• Specifies the level of physical synthesis optimization during fitting: Auto, Standard, Fast
• Auto—adjusts the Fitter optimization effort to minimize compilation time, while still achieving the
design timing requirements.
• Use the Auto Fit Effort Desired Slack Margin option to apply sufficient optimization effort to achieve
additional timing margin. It specifies the default worst-case slack margin the Fitter maintains for. If the
design is likely to have at least this much slack on every path, the Fitter reduces optimization effort to
reduce compilation time.
• Standard—use the Standard Fit option to exceed specified timing requirements and achieve the best
possible timing results and lowest routing resource utilization for your design
• For difficult designs, Auto and Standard both use maximum effort.
• Fast- The Fast Fit option reduces the amount of optimization effort for each algorithm employed during
fitting.
 6. OPTIMIZATION MODE

• The Compiler targets the optimization goal you specify using optimization mode.
• The settings affect synthesis and fitting.
• The following options direct the focus of Compiler optimization efforts during
synthesis:
1. Balanced (normal flow): The Compiler optimizes synthesis for balanced
implementation that respects timing constraints.
2. High Performance Effort: The Compiler increases the timing optimization effort
during placement and routing, and enables timing-related Physical Synthesis
optimizations (per register optimization settings). Each additional optimization can
increase compilation time.
 6. OPTIMIZATION MODE

3. High Performance with Maximum Placement Effort: Enables the same Compiler
optimizations as High Performance Effort, with additional placement optimization effort.
4. Superior Performance: Enables the same Compiler optimizations as High
Performance Effort, and adds more optimizations during Analysis & Synthesis to
maximize design performance with a potential increase to logic area. If design utilization
is already very high, this option may lead to difficulty in fitting, which can also
negatively affect overall optimization quality.
5. Superior Performance with Maximum Placement Effort: Enables the same
Compiler optimizations as Superior Performance, with additional placement optimization
effort.
 6. OPTIMIZATION MODE

6. Aggressive Area: The Compiler makes aggressive effort to reduce the device area
required to implement the design at the potential expense of design performance.
7. High Placement Routability Effort: The Compiler makes high effort to route the
design at the potential expense of design area, performance, and compilation time.
The Compiler spends additional time reducing routing utilization, which can
improve routability and also saves dynamic power.
8. High Packing Routability Effort: The Compiler makes high effort to route the
design at the potential expense of design area, performance, and compilation time.
The Compiler spends additional time packing registers, which can improve
routability and also saves dynamic power
 6. OPTIMIZATION MODE

9. Optimize Netlist for Routability: The Compiler implements netlist modifications

to increase routability at the possible expense of performance.
10. High Power Effort: The Compiler makes high effort to optimize synthesis for
low power. High Power Effort increases synthesis run time.
11. Aggressive Power: Makes aggressive effort to optimize synthesis for low power.
The Compiler further reduces the routing usage of signals with the highest specified
or estimated toggle rates, saving additional dynamic power but potentially affecting
performance.
12. Aggressive Compile Time: Reduces the compile time required to implement the
design with reduced effort and fewer performance optimizations
 7. OPTIMIZATION TECHNIQUE

• Specifies an overall optimization goal for Analysis & Synthesis.

• Optimization Technique Speed—optimizes timing-critical portions of your
design for performance at the cost of increasing area (logic and register
utilization)
• Optimization Technique Balanced—also optimizes the timing-critical
portions of your design for performance, but the option allows only limited
area increase
• Optimization Technique Area—optimizes your design only for area
 TIPS TO IMPROVING REGISTER-TO-
REGISTER TIMING (SLACK)

• The choice of options and settings to improve the timing margin (slack) or to
improve register-to-register timing depends on the failing paths in the design.
• Ensure that your timing assignments are complete. (Change Fitter Effort to
standard fit)
• Ensure that you have reviewed all warning messages from your initial
compilation, and have checked for ignored timing assignments.
• Apply netlist synthesis optimization options and physical synthesis. (Register
Duplication – ON, Physical Synthesis Register Duplication - ON)
• Try multiple different Fitter SEED
 IMPROVING REGISTER-TO-REGISTER
TIMING (SLACK)

• Optimize synthesis for speed not for area.

• Set synthesis effort to high.
• SPEED optimization technique.
• Set Maximum Router Timing Optimization Level.