CSC 211: COMPUTER

ORGANIZATION &
ASSEMBLY LANGUAGE
Lecture11 –Ref-Chapter09 –
Microcontrollers: The Atmel AVR

MS SAADIA KARIM
 CHAPTER OUTLINE

• ORGANIZATION AND ARCHITECTURE

• ASSEMBLY LANGUAGE
• MEMORY ORGANIZATION AND USE
• ISSUES OF INTERFACING
• DESIGNING AN AVR PROGRAM

2
 HISTORY
• A MICROCONTROLLER IS THE KIND OF COMPUTER USED FOR SMALL-SCALE
CONTROL OPERATIONS INSIDE DEVICES THAT ONE DOESN’T USUALLY THINK OF
AS BEING COMPUTERS.
• CLASSIC EXAMPLES OF SUCH DEVICES INCLUDE

3
 HISTORY

• FIRST,
• FOUND IN SO-CALLED EMBEDDED SYSTEMS,
• RUNNING SPECIALIZED SINGLE-PURPOSE CODE, USER-PROGRAMMABLE
COMPUTERS.

• SECOND,
• SMALLER,
• LESS CAPABLE COMPUTERS.

• THIRD, MICROCONTROLLERS ARE USUALLY

• SINGLE-CHIP GADGETS;
• THEIR MEMORY AND OTHER PERIPHERIAL INTERFACES ARE LOCATED ON
THE SAME PHYSICAL CHIP.0 4
 AVR MICROCONTROLLER

• AVR IS A FAMILY OF MICROCONTROLLERS DEVELOPED

SINCE 1996 BY ATMEL, ACQUIRED BY MICROCHIP
TECHNOLOGY IN 2016.
• THESE ARE MODIFIED HARVARD ARCHITECTURE 8-BIT RISC
SINGLE CHIP MICROCONTROLLERS.

5
 ORGANIZATION AND
ARCHITECTURE

• CENTRAL PROCESSING UNIT

• MEMORY
• DEVICES AND PERIPHERIALS
 CENTRAL PROCESSING UNIT

• THE ATMEL AVR USES RISC (REDUCED INSTRUCTION SET

COMPUTING) DESIGN PRINCIPLES IN THE INTERESTS OF BOTH
SPEED AND SIMPLICITY.
• EACH INSTRUCTION HAS
• STANDARDIZED LENGTH OF 16 BITS,
• INCLUDING THE NECESSARY ARGUMENTS.

• THE INSTRUCTION SET NEEDS MICROCONTROLLER,

• LARGE NUMBER OF BIT INSTRUCTIONS FOR THE MANIPULATION
OF INDIVIDUAL ELECTRICAL SIGNALS.
7
• ABOUT 130 DIFFERENT INSTRUCTIONS (FEWER THAN THERE ARE
ON THE JVM).
 MEMORY

• AVR IS A MICROCONTROLLER, ITS MEMORY ON AN AVR IS

QUITE LIMITED.
• AVR MEMORY IS DIVIDED INTO THREE SEPARATE BANKS
DEPENDING ON PHYSICALLY, SIZES AND CAPACITIES.
• FLASH MEMORY BANK (CODE STORAGE)
• SRAM BANK (SHORT TERM DATA STORAGE)
• EEPROM BANK (LONG TERM DATA STORAGE)

8
AVR block
architectur
e

9
Atmel AVR XMEGA Architecture

10
 KINDS OF MEMORY

• RAM (RANDOM ACCESS MEMORY)

• SRAM (STATIC RAM) & DRAM (DYNAMIC RAM)
• ROM (RANDOM ACCESS MEMORY)
• PROM (PROGRAMMABLE ROM)
• EPROM (ERASABLE PROGRAMMABLE ROM)
• EEPROM (ELECTRONICALLY ERASABLE PROGRAMMABLE ROM) OR
HYBRID MEMORY
• FLASH MEMORY
• NVROM (NON-VOLATILE RAM)
• SAM (SEQUENTIAL ACCESS MEMORY) 11
 DEVICES AND PERIPHERIALS

• AVR IMPLEMENTS A SIMPLE KIND OF MEMORY-MAPPED I/O.

• IT IS NOT DESIGNED TO BE USED IN GRAPHICS-HEAVY
ENVIRONMENTS.
• IT IS EXPECTED TO DRIVE A CHIP WHERE THE OUTPUT GOES
THROUGH A FEW PINS THAT ARE PHYSICALLY (AND
ELECTRICALLY) ATTACHED TO THE CPU CIRCUITRY.
• SPECIFICALLY, THESE PINS ARE ADDRESSABLE THROUGH
SPECIFIC DEFINED LOCATIONS IN THE I/O MEMORY BANK.

12
 ASSEMBLY LANGUAGE (1 OF 2)

• THE REGISTERS ON THE AVR ARE NOT STRUCTURED IN

ANY PARTICULAR FASHION.
• DIRECTLY CONNECTED TO ALL 32 GENERAL PURPOSE
REGISTERS.
• OPERATIONS BETWEEN REGISTERS EXECUTED WITH IN A
SINGLE CLOCK CYCLE.
• EG;
• ADD R0, R1 ; R0 = R0 + R1
13
 ASSEMBLY LANGUAGE (2 OF 2)

• SUPPORT ARITHMETIC, LOGIC, AND BIT FUNCTIONS.

• ADD, SUB, MUL (UNSIGNED MULTIPLY), MULS (SIGNED
MULTIPLY), INC, DEC, AND, OR, COM (BIT COMPLEMENT, I.E.,
NOT), NEG (TWO’S COMPLEMENT, I.E., NEGATE), EOR
(EXCLUSIVE OR), AND TST (WHICH TESTS A REGISTER
VALUE AND SETS THE FLAGS APPROPRIATELY IF THE VALUE
IS 0 OR NEGATIVE).
• THE AVR ALSO SUPPORTS INDIRECT JUMPS
(UNCONDITIONAL: IJMP, TO SUBROUTINE: ICALL) WHERE
14
THE TARGET LOCATION IS TAKEN FROM A REGISTER (PAIR),
SPECIFICALLY THE 16-BIT VALUE.
MEMORY ORGANIZATION AND USE (1 OF 3)

15
 MEMORY ORGANIZATION AND
USE (2 OF 3)
• REGISTERS:
• RX SPACE CONSISTS OF 32 GENERAL PURPOSE WORKING 8-BIT REGISTERS (R0-R31).
• THESE REGISTERS HAVE THE SHORTEST (FASTEST) ACCESS TIME, WHICH ALLOWS
SINGLE-CYCLE ARITHMETIC LOGIC UNIT (ALU) OPERATION.

• I/O MEMORY SPACE CONTAINS

• ADDRESSES FOR CPU PERIPHERAL FUNCTION, SUCH AS CONTROL REGISTERS, SPI,
AND OTHER I/O FUNCTIONS. 
• STORING DATA IN I/O AND EXTENDED I/O MEMORY IS HANDLED BY THE COMPILER
ONLY.
• USERS CAN NOT USE THIS MEMORY SPACE FOR STORING THEIR DATA. 

• INTERNAL SRAM (DATA MEMORY) IS USED FOR TEMPORARILY STORING AND

KEEPING INTERMEDIATE RESULTS AND VARIABLES (STATIC LINK AND DYNAMIC
LINK). 16
 MEMORY ORGANIZATION AND
USE (2 OF 3)
• THE AVR ALSO PROVIDES THREE SPECIFIC INDIRECT ADDRESS REGISTERS,
X, Y, AND Z, THAT CAN BE USED FOR INDIRECT ADDRESSING.
• IN ORDER TO WRITE TO THE EEPROM, THE PROGRAMMER SHOULD :
• LOAD THE BYTE ADDRESS OF INTEREST INTO THE EEAR.
• LOAD THE NEW DATA INTO THE EEDR.
• SET THE EEMWE TO 1, ENABLING WRITING TO THE EEPROM BANK.
• (WITHIN FOUR CLOCK CYCLES) SET THE EEWE TO 1, ALLOWING THE WRITE
TO HAPPEN.
• WRITE THE DATA.

17
 ISSUES OF INTERFACING

• INTERFACING WITH EXTERNAL DEVICES

• INTERFACING WITH TIMERS

18
INTERFACING WITH EXTERNAL
DEVICES

19
 INTERFACING WITH TIMERS

• A TIMER IS A SIMPLE COUNTER! THE INPUT CLOCK OF

MICROCONTROLLER AND OPERATION OF THE TIMER IS
INDEPENDENT OF THE PROGRAM EXECUTION.
• ALL THE ATMEL MICROCONTROLLERS HAVE TIMERS AS AN
INBUILT PERIPHERAL.

20
 DESIGNING AN AVR PROGRAM

• TRAFFIC SIGNAL EXAMPLE:

• IN ORDER FOR THIS TO WORK, A SET OF FOUR DIFFERENT PATTERNS MUST
BE PRESENTED:
• PATTERN NUMBER N/S LIGHT E/W LIGHT NOTES
• 0 GREEN RED TRAFFIC FLOWS N/S
• 1 YELLOW RED TRAFFIC SLOWING N/S
• 2 RED GREEN TRAFFIC FLOWS E/W
• 3 RED YELLOW TRAFFIC SLOWING E/W

• THE EASIEST WAY TO WRITE SUCH A PROGRAM IS TO IMPLEMENT WHAT’S

CALLED A STATE MACHINE.

21
THANKS

22