CHAPTER 3

INTRODUCTION TO IC
TESTING, RELIABILITY AND
FAILURE ANALYSIS
3.1 IC TESTING

Once assembled, the integrated circuit is ready to

use.  However, assembled devices don't always
work.

Many things can go wrong to make a device fail,

 The die has wafer fab-related defects

 The die cracked during assembly
 The bonds were poorly connected or not
connected at all.

Thus, prior to shipment to the customer, assembled

devices must first be electrically tested.
 3.1.1 Electrical Evaluation
TEST PATTERN

 Wafer testing is a step performed during semiconductor device fabrication.

 Testing is perform before the wafer is sent to die preparation.

 All individual integrated circuits that are present on the wafer are tested for functional defects by applying test
patterns process.

 The process of wafer testing can be referred to several ways :

 Wafer final test (WFT)

 Electronic die sort (EDS)
 Circuit probe (CP)
 3.1.1 Electrical Evaluation

PROBE TESTING

 A wafer prober is a machine (Automatic Test Equipment) used to test integrated circuit.

 For electrical testing a set of microscopic contacts or probes called probe card are held in place
while the wafer is vacuum mounted on a wafer chuck and moved into electrical contact.

 When a die ( or array of dice) have been electrically tested, the prober moves the wafer to the
next die (or array) and repeat the process.

 Most wafer prober are equipped with system to loading and unloading wafers from their carrier
or cassette

 An automatic pattern recognition optics are also equipped that capable of aligning the wafer
with sufficient accuracy to ensure accurate registration between the contacts pads on the wafer
and the tips of the probes.
 3.1.1 Electrical Evaluation

Types of Electrical Characterization

Electrical failures in general, can be divided into three areas:

(1) continuity failures

- failures such as ‘open’ and ‘short’
- the easiest to characterize

2) parametric failures
- inability of a device to meet the electrical specifications for a
measurable characteristics that does not directly pertain to its
functionality
- parametric characterization is also used to measure individual
component parameters such as bipolar transistor DC gain,
MOS transistor threshold voltage etc.
 3.1.1 Electrical Evaluation

(3) functional failures

- inability of a device to perform its intended function

- perform by inputting a known stimulus and measuring the

resulting outputs

- if the measured output states correspond to the expected

output states, the part is said to be functional. If not, the part is
failing functionally.
 3.1.2 Final (Product) Testing
 After wafer testing, the chips are separated by scoring a crosshatch of lines with a fine
diamond cutter onto the wafer.

 Those IC that are either damage during the process or which had failed the electrical test
before are discarded.

 Then, IC has been package with either ceramic or plastic based. These packages acts an
insulation layer to protect the IC as well as contain necessary leads which are used to connect
IC to the circuit bord.

 When the packaging completed, each IC must pass through one final test to determine if any
further chips damage during packaging process to gauge the performance of each device.

 The IC are tested depending on their expected use, therefore a chip which is to be used in a
high temperature environment, would have testing on the lines of probing a sample after it is
exposed to elevated temperatures for a period of time.
 3.1.3 Burn In

 Burn-in is an electrical stress test that employs voltage and

temperature to accelerate the electrical  failure of a device. 

 Burn-in essentially simulates the operating life of the device,

since the electrical excitation applied during burn-in may mirror
the worst-case bias that the device will be subjected to in the
course of its useable life. 

 Depending on the burn-in duration used,  the reliability

information obtained  may pertain to the device's early life or its
wear-out. 
 3.1.3 Burn In

• Burn-in is usually done at 125 deg C, with electrical

excitation applied to the samples. 
Figure 1
• The burn-in process is facilitated by using burn-in boards Photo of Bare and Socket-
populated Burn-in Boards
(see Fig. 1) where the samples are loaded.
• These burn-in boards are then inserted into the burn-in
oven (see Fig. 2), which supplies the necessary voltages
to the samples while maintaining the oven temperature at
125 deg C.  
• The electrical bias applied may either be static or
dynamic, depending on the failure mechanism being
accelerated.
Figure 2
Two examples of burn-in
ovens
 3.2 IC RELIABILITY &
DEGRADATION
3.2.1 Define Realibility

Reliability can be defined as the probability of a

device performing its purpose adequately for the
period of time intended under the specified conditions
encountered.
3.2.2 Reliability Prediction Techniques

 
 3.2.2 Reliability Prediction Techniques

Failure rate calculation example

Calculate the failure rate for a commercial product such as a washing machine that has
accumulated 5 failures that resulted in 5 service calls during 1,200 hours of operation.

Solution

5 failures/1,200 hours = 0.00417 failures per hour

In terms of scientific notation, the answer calculated above

is expressed as:
4170 failures/ 10 6hours or = 4,170 X 10-6

(failures per hour)

 3.2.2 Reliability Prediction Techniques

MTBF Example:

Calculate the MTBF for the previous example.

1/(0.00417) = 240 hours

This number becomes useful in that we can expect the machine to

break down after 240 hours of use, and this information can be
used to establish spares requirements.
3.2.3 Bath Tub Curve Prediction
 3.2.3 Bath Tub Curve Prediction

Represent the reliability performance of components.

Involves observing the reliability performance of a very large
sample of homogeneous components that is entering field service
or testing at the same start time, T=0.
 3.2.3 Bath Tub Curve Prediction

OBSERVING THE COMPONENTS OVER A LIFETIME, T

= TM (WHERE M REPRESENTS THE TIME AT THE END
OF LIFE), AND NOT REPLACE COMPONENTS WHEN
THEY FAIL, WE WOULD SEE 3 BASIC PERIODS OF
FAILURE PERFORMANCE:

1-INFANT MORTALITY (OR EARLY FAILURES)

2-RANDOM FAILURES (CONSTANT FAILURE RATE)
3-WEAROUT FAILURES (OR END OF LIFE FAILURES)
3.2.3 Bath Tub Curve Prediction
3.2.3 Bath Tub Curve Prediction
RANDOM FAILURES (USEFUL LIFE
PERIOD)
3.2.3 Bath Tub Curve Prediction

WEAROUT FAILURES
 3.3 MICROELECTRONIC FAILURE
ANALYSIS
1. DEFINE FAILURE ANALYSIS (FA) 4. FAILURE MECHANISM

FAILURE ANALYSIS IS THE PROCESS OF DETERMINING THE PHYSICAL PHENOMENON BEHIND THE FAILURE
HOW OR WHY A PRODUCT HAS FAILED. OF A PRODUCT.

EXAMPLE: METAL CORROSION, ELECTROSTATIC

DISCHARGE, ELECTRICAL OVERSTRESS
2. FAILURE TECHNIQUE

ARE SERIES STEPS TO DETERMINE HOW AND WHY A

PRODUCT HAS FAILED

2. ROOT CAUSE

3. FAILURE MODES THE FIRST EVENT OR CONDITION THAT TRIGGERED,

WHETHER DIRECTLY OR INDIRECTLY, THE
A DESCRIPTION OF HOW A PRODUCT IS FAILING,
OCCURRENCE OF THE FAILURE.
USUALLY IN TERMS OF HOW MUCH IT IS DEVIATING
FROM THE SPECIFICATION THAT IS FAILING. EXAMPLE : IMPROPER EQUIPMENT GROUNDING THAT
RESULTED IN ESD DAMAGE
EXAMPLE : EXCESSIVE SUPPLY CURRENT, EXCESSIVE
PFFSET VOLTAGE, EXCESSIVE BIAS CURRENT
 3.3.1 General Process Flow in FA

Product failure is defined as any non-conformance of the product to its electrical and/or
visual/mechanical specifications

 FA is necessary in order to understand what caused the failure and how it can be
prevented in the future

 Electrical failure can either be

(i) functional failure

• refers to the inability of a product to performs its intended functions

(ii) parametric failure

• refers to the inability of a product to meet certain electrical specifications, even if it
is able to able to perform its intended functions
3.3.1 General Process Flow in FA
Cause of Electronic Failures
 Typical Process Flow in FA
(1) Optical/Visual Inspection External visual inspection
looks for bent leads, package cracks, signs of heat damage or
lead corrosion.
(2) Electrical Tests
Functional testers or bench (lab) tests are performed to
identify the failure signature and reproduce the failure mode
if possible.
Temperature and voltage may be varied while testing
functionality and the effect on the parametric properties such
as I-V characteristics or access times are monitored.
In this case, the curve tracer is a cost-effective and important
tool for FA engineer. Typically, over one-third of the problem
can be isolated during the first two steps.
The test sequence followed for analyzing the remaining
two-thirds of the parts can take many different paths based
on the findings during the first two steps
(3) Non-electrical Tests
Non-electrical tests utilize radiographic methods such as
X-rays, Scanning Acoustic Microscopy (SAM) and
Thermal Imaging.
For example, in a thermal imager, an infrared microscope
detects the heat radiated from the device. This provides a
fast and easy technique for detecting hot spots due to die
attach problems, lead problems and bond wire shorts
(4) Decapsulation
The next stage is the destructive testing which begins
with decapsulation of the packaged device.
Decapsulation techniques, which are either chemical or
mechanical, are targeted at trying to prevent the process
from altering the defect, or modifying the electrical
signal.
 Typical Process Flow in FA
(5) First-rank Analytical Techniques
Following decapsulation, the chip is now exposed and should
still be electrically accessible, except for flip-chip mountings.
Imaging techniques such as optical microscopy, liquid crystal
analysis, electron-beam-induced current (EBIC) and optical-
beam-induced-current (OBIC) are a few of the powerful
techniques available
(6) Physical Techniques
The objective of the second stage of the analysis
once the failure location has been identified is to
determine the root cause of the failure.
Deprocessing or layer removal will positively
identify metal shorts or opens, silicon damage due
to electrical overstress and processing problems
such step coverage, and contact misalignment. This
can be done using either wet etching or dry etching.
At each relevant deprocessing step, Scanning
Electron Microscope (SEM) is used to view the
chip. SEM have the capability of 10,000 to 40,000
magnification and provides ~80% of all the FA
analysis.
 Typical Process Flow in FA
(8) Second-rank Analytical Techniques

These techniques are used mainly to study the material

properties of the failure location or defect site. Techniques
such as Energy Dispersive X-Ray (EDX) are used to
(7) Cross-Sectioning study the semiconductor surface and determine surface
contamination, presence of native oxides etc.
Defects in the wafer fab which are usually yield limiting are
analyzed using cross-sections through slices of the wafer. Energy-dispersive X-ray spectroscopy (EDS or EDX) is
an analytical technique used for the elemental analysis or
Problems with contacts, vias, interconnects, step coverage and chemical characterization of a sample
isolation are analyzed in this manner. Following cross-
sectioning, staining or etch decoration may be employed to
highlight areas with different dopant concentrations such as
junctions and isolations.

SEM or Transmission Electron Microscopy (TEM) are then

used to view the structure. More recently, Atomic Force
Microscope (AFM) have also been used to study cross-
sections
 Typical Process Flow in FA

(9) Third-rank Analytical Techniques

Analysis of the surface composition and near surface

properties of the Structure uses techniques which are
more specialist and are not usually found in an
engineering failure analysis lab.

Techniques such as Secondary Mass Ion Spectroscopy

(SIMS) are used to study surface defects and for
material analysis.
3.3.2 FA Techniques
3.3.2 FA Techniques
 3.3.2 FA Techniques

The FA process is finished once there are enough information to

make a conclusion about the location of the failure site and cause or
mechanism of failure

 Once the failure mechanism has been determined, the process

owner or expert can work with the failure analyst to determine the
root cause of the problem

 The process owner must always address the root cause of the
failure mechanism, not just the intermediate failure causes that
occurred after the root cause has already happened