COMPUTER

ARCHITECTURE 1
CPU Structure
A. S. Bah

BSc Information Systems – IPAM 1

Topics

Basic Functional Units of a Computer

Components of the CPU
ALU
Control Units
Register Array
System Bus

Main Memory (RAM)

Instruction execution - Complete Computer Unit

Instruction sets

Execution life cycle

A Simple Computer Architecture

Fetch Cycle

Decode Cycle

Execute Cycle

Summary - Execution life cycle

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Basic Functional Units of a Computer

Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

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 Components of the CPU
CPU (Central Processing Unit) is the brain of
the computer.

 It fetches and execute instruction

CPU consists of:

 Arithmetic and Logic Unit (ALU)
 Register Array
 Control Unit
 System Bus

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 Arithmetic and Logic Unit (ALU)
The ALU is the section of the processor that is
involved with executing operations of an
arithmetic or logical nature such as addition,
subtraction, and multiplication of integers and
Boolean operations.
It receives control signals from the control
unit telling it to carry out these operations.

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 The Register Array

A register is a memory location within the CPU itself, designed to be
quickly accessed for purposes of fast data retrieval

Processors normally contain a register array, which houses many such
registers. These contain instructions, data and other values that may
need to be quickly accessed during the execution of a program.

Many different types of registers are common between most
microprocessor designs. These are:
Program Counter (PC)
Instruction Register (IR)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Accumulator (A, or ACC)
Flag register / status flags
Other general purpose registers

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 The Register Array (Cont.)

Program Counter (PC)
This register is used to hold the memory address of the next instruction
that has to executed in a program. This is to ensure the CPU knows at all
times where it has reached, that is able to resume following an execution
at the correct point, and that the program is executed correctly.


Instruction Register (IR)
This is used to hold the current instruction in the processor while it is
being decoded and executed, in order for the speed of the whole
execution process to be reduced. This is because the time needed to
access the instruction register is much less than continual checking of
the memory location itself.

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 The Register Array (Cont.)
Memory Address Register (MAR)
Used for storage of memory addresses, usually the addresses involved in the
instructions held in the instruction register. The control unit then checks
this register when needing to know which memory address to check or
obtain data from

Memory Buffer Register (MBR)

When an instruction or data is obtained from the memory or elsewhere, it
is first placed in the memory buffer register. The next action to take is then
determined and carried out, and the data is moved on to the desired
location

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 The Register Array (Cont.)

Accumulator (A, or ACC)
The accumulator is used to hold the result of operations
performed by the arithmetic and logic unit


Flag register / status flags
The flag register is specially designed to contain all the
appropriate 1-bit status flags, which are changed as a result of
operations involving the arithmetic and logic unit


Other general purpose registers
These registers have no specific purpose, but are generally used
for the quick storage of pieces of data that are required later in
the program execution.

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 Control Unit
Controls the movement of instructions in and out of
the processor, and also controls the operation of the
ALU.

It is also responsible for performing the instruction

execution cycle

It consists of a decoder, control logic circuits, and a

clock to ensure everything happens at the correct time.

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 Control Unit (Cont.)
Decoder
The decoder is used to decode the instructions that make up a program when
they are being processed, and to determine what actions must be taken in
order to process them. These decisions are normally taken by looking at the
opcode of the instruction, together with the addressing mode used
Timer or clock
The timer or clock ensures that all processes and instructions are carried out
and completed at the right time. Pulses are sent to the other areas of the CPU
at regular intervals (related to the processor clock speed), and actions only
occur when a pulse is detected.
Control logic circuits
The control logic circuits are used to create the control signals themselves,
which are then sent around the processor. These signals inform
the arithmetic and logic unit and the register array what actions and steps
they should be performing, what data they should be using to perform said
actions, and what should be done with the results

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 System Bus
The system bus is a cable which carries data communication between
the major components of the computer, including the microprocessor.

The system bus consists of three different groups of wiring, called the
control bus, data bus and address bus.

Control Bus
The control bus carries the signals relating to the control and co-
ordination of the various activities across the computer, which can be
sent from the control unit within the CPU. Different architectures
result in differing number of lines of wire within the control bus, as
each line is used to perform a specific task. For instance, different,
specific lines are used for each of read, write and reset requests

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 System Bus (Cont.)
Data Bus
This is used for the exchange of data between the processor, memory and
peripherals, and is bi-directional so that it allows data flow in both directions
along the wires. The number of wires used in the data bus (sometimes known as
the 'width') can differ. Each wire is used for the transfer of signals corresponding
to a single bit of binary data. As such, a greater width allows greater amounts of
data to be transferred at the same time.
Address Bus
The address bus contains the connections between the microprocessor and
memory that carry the signals relating to the addresses which the CPU is
processing at that time, such as the locations that the CPU is reading from or
writing to. The width of the address bus corresponds to the maximum addressing
capacity of the bus, or the largest address within memory that the bus can work
with. The addresses are transferred in binary format, with each line of the address
bus carrying a single binary digit. Therefore the maximum address capacity is
equal to two to the power of the number of lines present (2^lines).

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 Main Memory (RAM)
The memory is not an actual part of the CPU itself,
and is instead housed elsewhere on the motherboard.
However, it is here that the program being executed is
stored, and as such is a crucial part of the overall
structure involved in program execution.

The memory stores program instructions or data for

only as long as the program they pertain to is in
operation.

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Instruction execution
Complete Computer Unit

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 Instruction execution (Cont.)
Software is installed onto a personal computer
Code comprising the program and any associated files is stored on the hard
drive
Code comprises of a series of instructions for performing designated tasks,
and data associated with these instructions
The code remains there until the user chooses to execute the program in
question, on which point sections of the code are loaded into the computer’s
memory
The CPU then executes the program from memory, processing each
instruction in turn
in order to execute the instructions, it is necessary for the CPU to
understand what the instruction is telling it to do. Therefore, recognition for
instructions that could be encountered needs to be programmed into the
processor. The instructions that can be recognized by a processor are referred
to as an 'instruction set', and are described in greater detail on the next slide

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 Instruction sets
For a processor to be able to process an instruction,
it needs to be able to determine what the instruction
is asking to be carried out. For this to occur, the CPU
needs to know what actions it may be asked to
perform, and have pre-determined methods available
to carry out these actions. It is this idea which is the
reasoning behind the 'instruction set‘

The instruction set is a collection of pre-defined

machine codes, which the CPU is designed to expect
and be able to act upon when detected

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 Instruction sets (Cont.)

Each machine code of an instruction set consist of two separate fields:

Opcode Operand(s)


The opcode is a short code which indicates what operation is expected
to be performed. Each operation has a unique opcode.


The operand, or operands, indicate where the data required for the
operation can be found and how it can be accessed. The length of a
machine code can vary - common lengths vary from one to twelve
bytes in size.

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 Instruction sets (Cont.)
If we are using a 24-bit CPU, then the minimum length
of the machine codes used here should be 24 binary bits,
which in this instance are split as shown in the table
below:

Opcode 6 bits (18-23) - Allows for 64 unique opcodes (2^6)

Operand(s) 18 bits (0-17) - 16 bits (0-15) for address values

- 2 bits (16/17) for specifying addressing mode to be used

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 Execution life cycle
Once a program is in memory it has to be executed. To do
this, each instruction must be looked at, decoded and acted
upon in turn until the program is completed. This is achieved
by the use of what is termed the 'instruction execution cycle',
which is the cycle by which each instruction in turn is
processed.
The instruction execution cycle can be clearly divided into
three different parts:
 Fetch Cycle
 Decode Cycle
 Execute Cycle
Before Discussing these execution cycles, let us take a quick
look at a simple Computer Architecture
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A Simple Computer Architecture

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 Fetch Cycle
The fetch cycle takes the address required from memory, stores
it in the instruction register, and moves the program counter
on one so that it points to the next instruction.
To fetch an instruction involves the following steps:
CPU must place an address to the MAR.
CPU must activate the tri-state buffer so MAR contents are placed on
the address bus.
CPU sends a read request to memory, to indicate it wants to do a read.
Memory eventually puts instruction on the data bus.
Memory sends ACK = 1.
CPU loads the instruction to the MBR.
CPU transfers instruction from MBR to IR.
PC is incremented by 1
CPU indicates to memory that it's done with fetching the instruction.

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 Decode Cycle
Once the instruction has been fetched and is stored in the
IR, the next step is to decode the instruction in order to
work out what actions should be performed to execute it.
This involves examining the opcode to see which of the
machine codes in the CPU's instruction set it corresponds
to, and also checking which addressing mode needs to be
used to obtain any required data.
Therefore, using the using the 24 bits CPU as example,
bits 18 to 23 should be examined
The instruction is then decoded in the IR
The Operand part of the instruction is transferred to the
MAR
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 Execute Cycle
Once the opcode is known, the execution cycle can occur.
Different actions need to be carried out dependant on the
opcode, with no two opcodes requiring the same actions to
occur. However, there are generally four groups of different
actions that can occur:
Transfer of data between the CPU and memory.
Transfer of data between the CPU and an input or output
devices.
Processing of data, possibly involving the use of the arithmetic
and logic unit.
A control operation, in order to change the sequence of
subsequent operations. These can possibly be conditional,
based on the values stored at that point within the flag register
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 Execute Cycle (Cont.)
Opcodes are also given mnemonics (short names) so that they
can be easily referred to in code listings and similar
documentationThese are:
MOV means moves a data value from one location to
another
ADD means adds to data values using the ALU, and
returns the result to the accumulator
STO means stores the contents of the accumulator in
the specified location
END means marks the end of the program in memory

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Summary - Execution life cycle

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Summary - Execution life cycle (Cont.)
Fetch
 Address of instruction is sent to memory through MAR
 Instruction received from memory and transferred to MBR
 Instruction carried to IR by MBR
 PC incremented by 1

Decode
 Instruction in IR are interpreted by Instruction Decoder by checking
the Opcode
Execute
 Instruction is carried out.

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 Concepts of Pipelining
Pipelining is the name given to the process by
which the processor can be working on more than
one instruction at once.
to consider the three stage fetch, decode and
execute instruction execution cycle.
There are times during each of these sub cycles of the
main cycle where the main memory is not being accessed,
and the CPU could be considered 'idle'. The idea,
therefore, is to begin the fetch stage for a second
instruction while the first stage is being decoded. Then,
when instruction one is being executed and instruction
two is being decoded, a third instruction can be fetched.
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 Pipelining Problems
While pipelining can severely cut the time taken to execute a
program, there are problems that cause it to not work as well as
it perhaps should. The three stages of the instruction execution
process do not necessarily take an equal amount of time, with
the time taken for 'execute' being generally longer than 'fetch'.
This makes it much harder to synchronise the various stages of
the different instructions. Also, some instructions may be
dependent on the results of other earlier instructions. This can
arise when data produced earlier needs to be used, or when a
conditional branch based on a previous outcome is used.
One of the simplest ways in which the effects of these problems
can be reduced is by breaking the instruction execution
cycle into stages that are more likely to be of an equal duration.

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 ?

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