ECEg-4261

Microelectronic Devices and Circuits

Chapter- 3
MOSFET
 Chapter Goals
• Describe structure and operation of MOSFETs.
• Define FET characteristics in operation regions of cutoff, triode and
saturation.
• Develop mathematical models for i-v characteristics of MOSFETs.
• Introduce graphical representations for output and transfer
characteristic descriptions of electron devices.
• Define and contrast characteristics of enhancement-mode and
depletion-mode FETs.
• Define symbols to represent FETs in circuit schematics.
• Investigate circuits that bias transistors into different operating
regions.
• Explore FET modeling in SPICE.
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
- amplifications (in analog)
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
- amplifications (in analog)
- switching (in digital)
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
- amplifications (in analog)
- switching (in digital)

• There are two basic types of solid state transistors: BJT (bipolar junction
transistor) and FET (field effect transistor).
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
- amplifications (in analog)
- switching (in digital)

• There are two basic types of solid state transistors: BJT (bipolar junction
transistor) and FET (field effect transistor).

• FET: electric field is used to control the shape and the conductivity of the
channel of one type charge carrier (p or n) in semiconductor device.
• They are also called unipolar to contrast their single-carrier-type operation with
the dual-carrier-type operation of bipolar (junction) transistors (BJT).
 Intro (1)

• Solid state transistor is the main building block of microelectronics.

• It performs two major functions used in electronic devices:
- amplifications (in analog)
- switching (in digital)

• There are two basic types of solid state transistors BJT (bipolar junction
transistor) and FET (field effect transistor).

• FET: electric filed is used to control the shape and hence the conductivity of
the channel of one type charge carrier (p or n) in semiconductor device.
• They are also called unipolar to contrast their single-carrier-type operation with
the dual-carrier-type operation of bipolar (junction) transistors (BJT).

• FET can be of two major types MOSFET (metal oxide semiconductor field
effect transistor (mostly used)), and JFET (junction field effect transistor).
 Intro (2)

• Metal Oxide Semiconductor Field Effect device was first solid state device
conceived (Lilienfield, 1928), however it took very long to develop a
successful commercial application of such devices. The first successful device
was fabricated in 1950, however the reliable commercial fabrication did not
start until decade later.
• Today, the CMOS technology based on MOSFET is the dominant technology
in electronics.
 Intro (2)

• Metal Oxide Semiconductor Field Effect device was first solid state device
conceived (Lilienfield, 1928), however it took very long to develop a
successful commercial application of such devices. The first successful device
was fabricated in 1950, however the reliable commercial fabrication did not
start until decade later.
• Today, the CMOS technology based on MOSFET is the dominant technology
in electronics.

• BJT devices were first introduced in 1948 and quickly became commercially
available. The first IC with logic gates and operational amplifiers that
appeared in early 1960s, were based on BJT technology. They are still widely
used, particularly in applications requiring high speed and high precision.

• BJT device is based on pn-junction structure, while MOSFET is utilizing the

MOS capacitor structure.
Metal Oxide Semiconductor
Field-Effect Transistors
(MOSFET)
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
• First electrode (Gate): low-resistivity
material such as metal or
polycrystalline silicon.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
• First electrode (Gate): low-resistivity
material such as metal or
polycrystalline silicon.
• Dielectric - Silicon dioxide: stable high-
quality electrical insulator between gate
and substrate.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
• First electrode (Gate): low-resistivity
material such as metal or
polycrystalline silicon.
• Dielectric - Silicon dioxide: stable high-
quality electrical insulator between gate
and substrate.
• Second electrode (Substrate, Body): n-
or p-type semiconductor.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
• First electrode (Gate): low-resistivity
material such as metal or
polycrystalline silicon.
• Dielectric - Silicon dioxide: stable high-
quality electrical insulator between gate
and substrate.
• Second electrode (Substrate, Body): n-
or p-type semiconductor.
• The semiconductor body has limited
supply of holes and electrons, and
substantial resistivity.
 MOS Capacitor Structure
• Metal Oxide Semiconductor capacitor is
the core structure of the a Metal Oxide
Semiconductor Field Effect Transistor.
• Consists of two electrodes and insulator
in between.
• First electrode (Gate): low-resistivity
material such as metal or
polycrystalline silicon.
• Dielectric - Silicon dioxide: stable high-
quality electrical insulator between gate
and substrate.
• Second electrode (Substrate, Body): n-
or p-type semiconductor. The concentration of carriers
• The semiconductor body has limited being dependant on voltage, the
supply of holes and electrons, and capacitance of this structure
substantial resistivity. therefore is a nonlinear function
of voltage applied.
Substrate Conditions for Different Biases
We consider the conditions of the semiconductor region (p-type) below the gate
electrode under three different voltage bias: accumulation, depletion, inversion.
Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at
which the electron inversion layer is just starting to form.
• Accumulation : VG<<VTN
The majority carriers (holes) accumulate in
a very thin layer below the negative gate
(like in capacitor)
Substrate Conditions for Different Biases
We consider the conditions of the semiconductor region (p-type) below the gate
electrode under three different voltage bias: accumulation, depletion, inversion.
Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at
which the electron inversion layer is just starting to form.
• Accumulation : VG<<VTN , VG<0
The majority carriers (holes) accumulate in
a very thin layer below the negative gate
(like in capacitor)

• Depletion: 0<VG<VTN
The small positive charge of the gate wipe
out the holes from the layer below
(depletes free carriers) creative a negative
charge of ionized atoms
Substrate Conditions for Different Biases
We consider the conditions of the semiconductor region (p-type) below the gate
electrode under three different voltage bias: accumulation, depletion, inversion.
Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at
which the electron inversion layer is just starting to form.
• Accumulation : VG<<VTN
The majority carriers (holes) accumulate in
a very thin layer below the negative gate
(like in capacitor)

• Depletion: 0<VG<VTN
The small positive charge of the gate wipe
out the holes from the layer below
(depletes free carriers) creative a negative
charge of ionized atoms

• Inversion: VG>VTN
The larger positive charge of the gate
attracts electrons whose concentration in
the very thin layer exceeds that of holes –
inversion of p-type into n-type.
Low-frequency C-V Characteristics for
MOS Capacitor on P-type Substrate
• MOS capacitance is non-linear
function of voltage.

• Total capacitance in any region is

dictated by the separation between
capacitor plates.

• Total capacitance can be modeled as

series combination of fixed oxide
capacitance and voltage-dependent
depletion layer capacitance.
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D)
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D),
Source(S)
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D),
Source(S)
Body(B)
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D),
Source(S)
Body(B).
• Source and drain regions form
pn junctions with substrate.
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D),
Source(S)
Body(B).
• Source and drain regions form
pn junctions with substrate.
• vSB,= vS – vB , vDS = vD - vS and vGS
= vG - vS are typically
nonnegative during normal
operation.
 NMOS Transistor: Structure
A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of
silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting
diffusions provide a supply of electrons that can rapidly form the inversion layer and easily
move under the gate, and also make terminals to apply a voltage and create a current in the
channel region.
• 4 device terminals:
Gate(G)
Drain(D),
Source(S)
Body(B).
• Source and drain regions form
pn junctions with substrate.
• vSB,= vS – vB , vDS = vD - vS and vGS
= vG - vS are always positive
during normal operation.
• vB <= vD and vB <= vS , to keep
pn junctions reverse biased.
NMOS Transistor and Variable Resistor
• A transistor is a three (or four)
terminal device, in which one
terminal controls the voltage or
current between other two
terminals
• In certain way it is similar to a
variable resistor, in which the
movement of the middle terminal
controls the voltage.

- -
NMOS Transistor: Qualitative Behavior @ vDS =0

• VGS<<VTN (VGS <0): Two back to back

reverse biased pn junctions btw S and
D. Only small leakage current flows.
NMOS Transistor: Qualitative Behavior @ vDS =0

• VGS<<VTN (VGS <0): Two back to back

reverse biased pn junctions btw S and
D. Only small leakage current flows.

• VGS<VTN (VGS >0): Depletion region

formed under gate merges with source
and drain depletion regions. No
current flows between source and
drain.
NMOS Transistor: Qualitative Behavior @ vDS =0

• VGS<<VTN (VGS <0): Two back to back

reverse biased pn junctions btw S and
D. Only small leakage current flows.

• VGS<VTN (VGS >0): Depletion region

formed under gate merges with source
and drain depletion regions. No
current flows between source and
drain.

• VGS>VTN: Channel is formed between

source and drain by electrons in
inversion layer. If VDS>0, finite iD
flows from drain to source.

• iB=0 and iG=0.

NMOS Transistor: Qualitative Behavior @ vDS =0

Since the induced inversion layer is formed by electrons, it’s called N-channel
MOSFET.
 NMOS Transistor: Triode Region
Applying a small vDS creates a flow of electrons in the induced inversion layer between
source and drain - current iD (iD = iS , since iB=0 and iG=0).

 v 
i  Kn v V 
 DS v
D GS TN



2  DS
v  small
DS

for 0  v v V
DS GS TN
where
Kn= Kn’W/L – the gain factor
Kn’=mnCox’’ (A/V2)
Cox’’=ox/Tox
 ox= oxide permittivity (F/cm)
Tox = oxide thickness (cm)
This is the triode region (linear region, ohmic mode).  
MOSFET operates like a resistor, controlled by the gate voltage relative to both the
source and drain voltages.
 N-MOS Transistor: Triode Region
(derivation of the source-drain current)
Since currents iB and iG both are zero, and there is no path for drain current to escape: iS = iD.
To find it, we consider the transport of the charge. The linear density of the electron charge
at any point in the channel is:

Q '  W Cox ''(vox  VTN ) C / cm for vox  VTN ,

where Cox ''   ox / Tox  oxide capacitance per area,  ox  oxide permittivity(F/cm), Tox  oxide thickness (cm)

The voltage vox is the function of position x in the channel: vox  vGS  v(x). For inversion layer to
exist, should be vox > VTN , so Q’ = 0 until vox > VTN . At the source, vox = vGS and it decrease to
vox = vGS - vDS at the drain.
dv( x)
i ( x)  Q ' v x   W Cox ' ' (vox  VTN )(  n E x ) Ex  
The electron drift current is : , where dx

dv( x)
i ( x)    n Cox ' 'W vGS  v ( x)  VTN 
Combining
L
everything:
v
dx and integrating:
 i ( x )dx     n Cox "W vGS  v( x )  VTN dv( x)
DS

0 0 , we get
W v   v 
iD   nCox "  vGS  VTN  DS  vDS  K n  vGS  VTN  DS 
L 2   2 
W
where K n  K n' , and K n'   n Cox''
L
 Triode (a bit of history)
A triode is an electronic amplification device having three active electrodes.
most commonly it’s a vacuum tube with three elements: the filament (cathode),
the  grid (controlling element), and the plate or anode. The triode vacuum tube
was the first electronic amplification device. It’s iv-characteristics was quite
linear.
 N-MOSFET: Triode Region Characteristics
 v 
• The expression for iD is quadratic in vDS i  Kn v V  DS  v

D 

GS TN 2  DS
 N-MOSFET: Triode Region Characteristics
 v 
• The expression for iD is quadratic in vDS i  Kn v V  DS  v

D 

GS TN 2  DS
with max reached at vDS = vGS - vTN = vOV

vDS
 N-MOSFET: Triode Region Characteristics
 v 
• The expression for iD is quadratic in vDS i  Kn v V  DS  v

D 

GS TN 2  DS
with max reached at vDS = vGS - vTN = vOV
• For small vDS << vGS - vTN , the
characteristics iD vs. vDS appear to be linear
(triode region, linear)

vDS
 N-MOSFET: Triode Region Characteristics
• The expression for iD is quadratic in vDS Under this condition, MOSFET
with max reached at vDS = vGS - vTN = vOV behaves like a
gate-source voltage-controlled
• For small vDS << vGS - vTN , the
resistor between source and
characteristics iD vs. vDS appear to be linear
drain,
(triode region, linear)
i  Kn  v V  v  1 v
D  GS TN  DS Ron DS
 N-MOSFET: Triode Region Characteristics
• The expression for iD is quadratic in vDS Under this condition, MOSFET
with max reached at vDS = vGS - vTN = vOV behaves like a
gate-source voltage-controlled
• For small vDS << vGS - vTN , the
resistor between source and
characteristics iD vs. vDS appear to be linear
drain,
(triode region, linear)
i  Kn  v V  v  1 v
D  GS TN  DS Ron DS

where on-resistance:

1
Ron 
W
K n ' VGS VTN VDS 
L 
v DS 0

 1  Ron (V )
Kn 'W V V  GS
L  GS TN 
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
v Ron 1
vo  G(VGS )vs , G(VGS )  o  
vs Ron  R 1 K R V  V 
n  GS TN 

If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V:

MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
v Ron 1
vo  G(VGS )vs , G(VGS )  o  
vs Ron  R 1 K R V  V 
n  GS TN 

If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V:

G(VGS  1)  1 1
A
2000  11 V
2
1 500
V
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
v Ron 1
vo  G(VGS )vs , G(VGS )  o  
vs Ron  R 1 K R V  V 
n  GS TN 

If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V:

G(VGS  1)  1 1
A
2000  11 V
2
1 500
V
G(VGS  2)  1  0.5
A
2000   21 V
2
1 500
V
MOSFET as Voltage-Controlled Resistor
Example: Voltage-Controlled Attenuator
v Ron 1
vo  G(VGS )vs , G(VGS )  o  
vs Ron  R 1 K R V  V 
n  GS TN 

If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V:

G(VGS  1)  1 1
A
2000  11 V
2
1 500
V
G(VGS  2)  1  0.5
A
2000   21 V
2
1 500
V
G(VGS  1.5)  1  0.667
A
2000  1.51 V
2
1 500
V
To maintain triode region operation,
v  v V or vo  V V
DS GS TN GS TN
 NMOS Transistor: inversion layer change
If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it
starts influencing the depth of induced inversion layer, for which we need VGS > VTN.
VOV - overdrive voltage
 NMOS Transistor: inversion layer change
If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it
starts influencing the depth of induced inversion layer, for which we need VGS > VTN.
VOV - overdrive voltage

vDS = VOV - pinch-off voltage, saturation region begins

 NMOS Transistor: Saturation Region

What is the current in

saturation region?
• When vDS increases above triode region
limit, channel region akmost
disappears, MOSFET also said to be
pinched-off.
• Current saturates at (almost) constant
value, independent of vDS.

v  v V
DSAT GS TN is also called
saturation or pinch-off voltage.
 NMOS Transistor: Saturation Region
Substituting vDS = vGS - VTN
into previous equation for
drain current, we get
K' W 2
i  n  v V 
D TN 
• When vDS increases above triode region 2 L  GS
limit, channel region akmost
disappears, MOSFET also said to be for vDS  vGS VTN
pinched-off.
• Current saturates at (almost) constant
value, independent of vDS. • Saturation region operation
mostly used for analog
v  v V amplification.
DSAT GS TN is also called
saturation or pinch-off voltage.
NMOS Transistor: iv-characteristic

vGS  v( x po )  VTN
NMOS Transistor: Region Summary
• If vDS << VGS - VTN MOSFET is in linear
portion of the triode region

Triode
NMOS Transistor: Region Summary
• If vDS << VGS - VTN MOSFET is in linear
portion of the triode region
• If vDS < VGS - VTN MOSFET is in quadratic
portion of the triode region
NMOS Transistor: Region Summary
• If vDS << VGS - VTN MOSFET is in linear
portion of the triode region
• If vDS < VGS - VTN MOSFET is in
quadratic portion of the triode region
• If vDS < VGS - VTN MOSFET is in saturation
region and current saturates at (almost)
constant value, independent of vDS.
 Transconductance of a MOS Device
• Transconductance is the important characteristics that
relates the change in drain current to a change in gate-
source voltage di
D
gm 
dv
GS Q pt


 Transconductance of a MOS Device
• Transconductance is the important characteristics that
relates the change in drain current to a change in gate-
source voltage di
D
gm 
dv
GS Q pt
• Taking the derivative of the expression for the drain
current in saturation region,


W 2I
gm  Kn' (V V ) D
L GS TN V V
GS TN


 Transconductance of a MOS Device
• Transconductance is the important characteristics that
relates the change in drain current to a change in gate-
source voltage di
D
gm 
dv
GS Q pt
• Taking the derivative of the expression for the drain
current in saturation region,


W 2I
gm  Kn' (V V ) D
L GS TN V V
GS TN
• The larger the device transconductance, the more gain we

can expect from the amplifier that uses the transistor.
• Transconductance is inverse to the Ron defined earlier and
slightly differently.
Channel-Length Modulation
• On the previous iv-characteristics, the
saturation part was horizontal (the current
was constant, as vDS increases). However, it’s
not exactly so.
Channel-Length Modulation
• On the previous iv-characteristics, the
saturation part was horizontal (the current
was constant, as vDS increases). However, it’s
not exactly so.
• As vDS increases above vDSAT , length of
depleted channel beyond pinch-off point, DL,
increases and actual L decreases.
 Channel-Length Modulation
• On the previous iv-characteristics, the
saturation part was horizontal (the current
was constant, as vDS increases). However, it’s
not exactly so.
• As vDS increases above vDSAT , length of
depleted channel beyond pinch-off point, DL,
increases and actual L decreases.
• Since L is in denominator of the current
expression, it compensate slightly the general
increase of resistivity, which normally makes
the curve flat.

K' W 2
i  n  v V 
D TN 
2 L  GS
 Channel-Length Modulation
• On the previous iv-characteristics, the
saturation part was horizontal (the current
was constant, as vDS increases). However, it’s
not exactly so.
• As vDS increases above vDSAT , length of
depleted channel beyond pinch-off point, DL,
increases and actual L decreases.
• Since L is in denominator of the current
expression, it compensate slightly the general
increase of resistivity, which normally makes
the curve flat.
• As a result, iD increases slightly with vDS
instead of being constant and we can rewrite
equation in the form:
K' W 2 K 'W 2
i  n  v V  i  n  v V  1 v 
D TN 
2 L  GS
D  GS TN   DS 
2 L
Channel-Length Modulation
• On the previous iv-characteristics, the
saturation part was horizontal (the current
was constant, as vDS increases). However, it’s
not exactly so.
• As vDS increases above vDSAT , length of
depleted channel beyond pinch-off point, DL,
increases and actual L decreases.
• Since L is in denominator of the current
expression, it compensate slightly the general
increase of resistivity, which normally makes
the curve flat.
• As a result, iD increases slightly with vDS
instead of being constant and we can rewrite
equation in the form:
K 'W 2
i  n  v V  1 v 
D  GS TN   DS 
2 L
where l is the channel length modulation
parameter, depends on manufacturing and L.
Va – Early voltage.
Enhancement and Depletion Mode MOSFETS
• The MOSFETS transistors can be of two types:
enhancement mode when VTN > 0
Enhancement and Depletion Mode MOSFETS
• The MOSFETS transistors can be of two types:
enhancement mode when VTN > 0
depletion mode when VTN < 0
(the NMOS transistors considered so far were of enhancement type.)
Enhancement and Depletion Mode MOSFETS
• The MOSFETS transistors can be of two types:
enhancement mode when VTN > 0
depletion mode when VTN < 0
(the NMOS transistors considered so far were of enhancement type.)
• The depletion mode devices are fabricated by ion implantation process
used to form a built-in n-type channel in device to connect source and
drain by a resistive channel.
Enhancement and Depletion Mode MOSFETS
• The MOSFETS transistors can be of two types:
enhancement mode when VTN > 0
depletion mode when VTN < 0
(the NMOS transistors considered so far were of enhancement type.)
• The depletion mode devices are fabricated by ion implantation process
used to form a built-in n-type channel in device to connect source and
drain by a resistive channel.
• In such case, a non-zero drain current exists for vGS=0, and a
negative vGS required to turn device off.
Enhancement and Depletion Mode MOSFETS
• The MOSFETS transistors can be of two types:
enhancement mode when VTN > 0
depletion mode when VTN < 0
(the NMOS transistors considered so far were of enhancement type.)
• The depletion mode devices are fabricated by ion implantation process
used to form a built-in n-type channel in device to connect source and
drain by a resistive channel.
• In such case, a non-zero drain current exists for vGS=0, and a
negative vGS required to turn device off.

Depletion mode – because negative

voltage has to be applied to the gate to
deplete the n-type channel and
eliminate the current path between the
source and the drain.
Output and Transfer Characteristics of MOSFETS
• A MOSFET has one output variable – the drain-source current , that
depends on two input variables – drain-source voltage and gate-source
voltage (VGS is usually is a control variable).
Output and Transfer Characteristics of MOSFETS
• A MOSFET has one output variable – the drain-source current , that depends
on two input variables – drain-source voltage and gate-source voltage (VGS
is usually is a control variable).
• Two types of iv-curves are used to describe a MOSFET device fully:
output (drain) curve (DS current vs. DS voltage for a fixed GS voltage)
(the earlier considered characteristics were drain curves)
 Output and Transfer Characteristics of MOSFETS
• A MOSFET has one output variable – the drain-source current , that depends
on two input variables – drain-source voltage and gate-source voltage (VGS is
usually is a control variable).
• Two types of iv-curves are used to describe a MOSFET device fully:
output (drain) curve (DS current vs. DS voltage for a fixed GS voltage)
(the earlier considered characteristics were drain curves)
transfer curve (DS current vs. GS voltage for a fixed DS voltage, f.i. sat.)

Curves show that the enhancement mode device turns on at

VGS = 2, while the depletion mode device turns on at VGS = -2.
Example here
 Body Effect or Substrate Sensitivity
So far it was assumed that the source-bulk voltage vSB , is zero, which means that a
MOSFET is a three terminal device. Quite often vSB , especially in ICs is not zero..
• Non-zero vSB changes threshold voltage.
• This is called substrate sensitivity and is
modeled by
 
V V   v 2  2 
TN TO  SB F F 
where

VTO - zero substrate bias for VTN (V)
g - body-effect parameter ( V )m,
determines the intensity of the body
effect 

2FF - surface potential parameter (V),

typically 0.6V.
NMOS Summary (output characteristics)
PMOS Transistors Structure (Enhancement-Mode)
0 0

ID

PMOS NMOS

• p-type source and drain regions in • n-type source and drain regions in
n-type substrate. p-type substrate.
PMOS Transistors Structure (Enhancement-Mode)
0 0

ID

PMOS NMOS

• P-type source and drain regions in • N-type source and drain regions in
n-type substrate. p-type substrate.
• vGS < 0 required to create p-type • vGS > 0 required to create n-type
inversion layer in channel region inversion layer in channel region
PMOS Transistors Structure (Enhancement-Mode)
0 0

ID

PMOS NMOS

• P-type source and drain regions in
n-type substrate.
• vGS < 0 required to create p-type
inversion layer in channel region
• For current flow, vGS<vTP
• N-type source and drain regions in
p-type substrate.
• vGS > 0 required to create n-type
inversion layer in channel region
• For current flow, vGS > vTN
PMOS Transistors Structure (Enhancement-Mode)
PMOS
• P-type source and drain regions in
n-type substrate.
• vGS < 0 required to create p-type
inversion layer in channel region
• For current flow, vGS<vTP
• To maintain reverse bias on diodes
of source-substrate and drain-
substrate junctions:
vSB < 0 and vDB < 0
0 0
ID
NMOS
• N-type source and drain regions in
p-type substrate.
• vGS > 0 required to create n-type
inversion layer in channel region
• For current flow, vGS > vTN
• To maintain reverse bias on the
diodes of source-substrate and
drain-substrate junctions:
vSB >0 and vDB >0
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
• Thus the output characteristics of PMOS
are the complete inverse of those of NMOS
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
• Thus the output characteristics of PMOS
are the complete inverse of those of NMOS
• Often, they are shown in the inverted scale
and then they look very similar to the
characteristics of NMOS
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
• Thus the output characteristics of PMOS
are the complete inverse of those of NMOS
• Often, they are shown in the inverted scale
and then they look very similar to the
characteristics of NMOS

• For VGS VTP , transistor is off (note

that on the diagram it’s vSG = - vGS).

Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
• Thus the output characteristics of PMOS
are the complete inverse of those of NMOS
• Often, they are shown in the inverted scale
and then they look very similar to the
characteristics of NMOS

• For VGS VTP , transistor is off (note

that on the diagram it’s vSG = - vGS).


• For more negative vGS, drain current

increases in magnitude.
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For the PMOS transistor, all parameters and
behavior are inverse of NMOS transistor.
• Thus the output characteristics of PMOS
are the complete inverse of those of NMOS
• Often, they are shown in the inverted scale
and then they look very similar to the
characteristics of NMOS

• For VGS VTP , transistor is off (note

that on the diagram it’s vSG = - vGS).


• For more negative vGS, drain current

increases in magnitude.
• PMOS is in triode region for small
(absolute) values of VDS and in
saturation for larger values (note that
on the diagram it’s more negative to
the right).
 NMOS Summary (model)

For the enhancement-mode NMOS transistor, VTN > 0. For the depletion-mode NMOS, VTN < 0.
 PMOS Summary (model)

For the enhancement-mode PMOS transistor, VTP < 0. For the depletion-mode PMOS, VTP > 0.
NMOS and PMOS Summary (regions of operation)
NMOS and PMOS Summary (terminal voltages)
 Short Summary of MOSFET (1)
• A MOSFET is a 3 terminal (Gate, Source, Drain) or 4 terminal (Gate, Source, Drain,
Body) electronic device -- it has input (usually vGS) and output (usually iD).

• The basic function of all transistors - an input voltage is used to provide the change in
the output current (or voltage):
– the change in output can be much bigger then the change in the input - amplifier
– the change in output can be to turn it on or off – digital gate

• There are two types of MOSFET : PMOS and NMOS

• Both types exist in two modes: Enhancement and Depletion.

• NMOS enhancement mode: the output current (the inversion channel) may exist only
when input (vGS ) is positive (>0).
• NMOS depletion mode: the output current (the inversion channel) may exist when input
(vGS ) is zero, requires to apply vGS <0 to shut the current).

• PMOS is pretty much the complete inverse of NMOS.

 Short Summary of MOSFET (2)

NMOS PMOS
Body: p-substrate Body: n-substrate
Source, Drain: n+ Source, Drain: p+
Inversion (conduction) layer: n Inversion (conduction) layer: p

E-NMOS D-NMOS E-PMOS D-PMOS

Channel Channel Channel Channel
(drain current (drain current (drain current (drain current
exists exists exists exists
when vGS > 0) when vGS = 0) when vGS < 0) when vGS = 0)

VTN > 0 VTN <= 0 VTP < 0 VTP >= 0

 Short Summary of MOSFET (3)
• MOSFET is a symmetrical device – D and S are interchangeable.
• MOSFET is fully described by two characteristics:
- input-output or transfer characteristic: (iD - vGS or vDS - vGS )
- output characteristic: (iD – vDS )
• All four types of MOSFET may operate in three regions:
- cutoff : output current is 0
- triode: output current almost linearly depends on output voltage vDS (like in resistor)
- saturation: output current almost does not depend on DS voltage vDS (like in diode)

Transfer characteristics Output characteristics

MOSFET Circuit Symbols

• (g) and (i) are the most

commonly used symbols in VLSI
logic design.
• MOS devices are symmetric.
• In NMOS, n+ region at higher
voltage is the drain.
• In PMOS p+ region at lower
voltage is the drain
 MOSFET Analysis
• Depending on the type of application, a MOSFET may be put into one of three
regions of operation by setting its operating Q-point .
 MOSFET Analysis
• Depending on the type of application, a MOSFET may be put into one of three
regions of operation by setting its operating Q-point.
• For binary logic application the transistor acts like an “on-off” switch and the
Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for
the output characteristic or at the ends of transfer characteristic.
 MOSFET Analysis
• Depending on the type of application, a MOSFET may be put into one of three
regions of operation by setting its operating Q-point.
• For binary logic application the transistor acts like an “on-off” switch and the
Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for
the output characteristic or at the ends of transfer characteristic.
• For amplifier application, the Q-point is set in the saturation region for the
output characteristic or in the middle (high) point of the transfer characteristic
 MOSFET Analysis: logic inverter example
• For the low values of input vGS (binary 0) the =0

MOSFET is off, iD =0 and vDS = vout = 5V 

binary 1.
=5

=low
 MOSFET Analysis: logic inverter example
=high

=0.6
• For vGS =5V (binary 1) the MOSFET is on, iD is
high, and the output voltage vDS = vout = 0.65V  =5

binary 0.
 MOSFET Analysis: logic inverter example
• For the low values of input vGS (binary 0) the =0
=high
MOSFET is off, iD =0 and vDS = vout = 5V 
binary 1. =5
=0.6
• For vGS =5V (binary 1) the MOSFET is on, iD is
=low
high, and the output voltage vDS = vout = 0.65V  =5

binary 0.
 MOSFET Analysis: amplifier example
• For the amplifier, the Q-point created by
vGS = 2.5V is located at the high slope region
of transfer characteristic and at the saturation
region of the 2.5V curve.

=2. 5
 MOSFET Analysis: amplifier example
• For the amplifier, the Q-point created by
vGS = 2.5V is located at the high slope region
of transfer characteristic and at the saturation
region of the 2.5V curve.
• A small AC signal is added to vary the gate
voltage about vGS = 2.5V, which causes the =2. 5
drain current to change significantly and
amplified replica of the input appears at the
drain.
 MOSFET Analysis: load line example
Thevenin
• From KVL for the right loop: equivalent

vDD - vDS - iD RD = 0  iD = (vDD - vDS )/RD Nonlinear

element
• Setting two different values for vDS (5V and
3V for example) two points can be obtained
and the load line drawn.
 MOSFET Analysis: load line example
Thevenin
• From KVL for the right loop: equivalent

vDD - vDS - iD RD = 0  iD = (vDD - vDS )/RD Nonlinear

element
• Setting two different values for vDS (5V and
3V for example) two points can be obtained
and the load line drawn.
• Intersection with the transistor iv-curve
gives the Q-point, which, of course, depends
on the input vGS.

Conclusion
• The same device in the similar circuits may
behave differently depending on the
‘biasing‘ – DC voltages applied to different
terminals of MOSFET. The ‘signal’ then, is
actually comprised of relatively small
changes in the DC current and/or voltage
bias.
 Bias Analysis Approach
• The previous examples shows the importance of biasing for the desired
operation of MOSFET.
• Because of nonlinearity of characteristics and substantial difference in
operation region equations (different equations used), iterative approach is
used:
 Bias Analysis Approach
• The previous examples shows the importance of biasing for the desired
operation of MOSFET.
• Because of nonlinearity of characteristics and substantial difference in
operation region equations (different equations used), iterative approach is
used:

• Assume an operation region (generally the saturation region)

 Bias Analysis Approach
• The previous examples shows the importance of biasing for the desired
operation of MOSFET.
• Because of nonlinearity of characteristics and substantial difference in
operation region equations (different equations used), iterative approach is
used:

• Assume an operation region (generally the saturation region)

• Use circuit analysis to find VGS (left, input loop)
 Bias Analysis Approach
• The previous examples shows the importance of biasing for the desired
operation of MOSFET.
• Because of nonlinearity of characteristics and substantial difference in
operation region equations (different equations used), iterative approach is
used:

• Assume an operation region (generally the saturation region)

• Use circuit analysis to find VGS (left, input loop)
• Use VGS to calculate ID, and ID to find VDS (right, output loop)
 Bias Analysis Approach
• The previous examples shows the importance of biasing for the desired
operation of MOSFET.
• Because of nonlinearity of characteristics and substantial difference in
operation region equations (different equations used), iterative approach is
used:

• Assume an operation region (generally the saturation region)

• Use circuit analysis to find VGS (left, input loop)
• Use VGS to calculate ID, and ID to find VDS (right, output loop)
• Check validity of operation region assumptions
• Change assumptions and analyze again if required.

NOTE : An enhancement-mode device with VDS = VGS is always in saturation.

Why? For pinch off: VDS >= VGS - VTN . If VDS = VGS , then VDS >= VDS - VTN , or VTN >= 0, which is
always true for E-MOS device.
Bias Analysis 1- Constant GS Voltage Biasing (1)

Problem: Find Q-pt (ID, VDS , VGS)

without and with the channel-length
modulation (   0 and   0.02V ).
1

Approach: Assume operation

region, find Q-point, check to see if
result is consistent with operation
region.
Bias Analysis 1- Constant GS Voltage Biasing (1)

Problem: Find Q-pt (ID, VDS , VGS)

without and with the channel-length
modulation (   0 and   0.02V ).
1

Approach: Assume operation

region, find Q-point, check to see if
result is consistent with operation
region.
Assumption:
1. Transistor is saturated.
2. IG=IB=0.
Bias Analysis: Ex.1- Constant GS Voltage Biasing (1)

Problem: Find Q-pt (ID, VDS , VGS)

Analysis:
without and with the channel-length
modulation (   0 and   0.02V ).
1
Simplify circuit with Thevenin
transformation to find VEQ and REQ for
Approach: Assume operation
region, find Q-point, check to see if gate-bias voltage.
result is consistent with operation
region.
Assumption:
1. Transistor is saturated.
2. IG=IB=0.
Bias Analysis 1- Constant GS Voltage Biasing (1)

Problem: Find Q-pt (ID, VDS , VGS)

Analysis:
without and with the channel-length
modulation (   0 and   0.02V ).
1
Simplify circuit with Thevenin
transformation to find VEQ and REQ for
Approach: Assume operation
region, find Q-point, check to see if gate-bias voltage.
result is consistent with operation Find VGS from the input loop, and then
region. use this to find ID.
Assumption:
1. Transistor is saturated.
2. IG=IB=0.
Bias Analysis 1- Constant GS Voltage Biasing (1)

Problem: Find Q-pt (ID, VDS , VGS)

Analysis:
without and with the channel-length
modulation (   0 and   0.02V ).
1
Simplify circuit with Thevenin
transformation to find VEQ and REQ for
Approach: Assume operation
region, find Q-point, check to see if gate-bias voltage.
result is consistent with operation Find VGS from the input loop, and then
region. use this to find ID.
Assumption: With ID, we can then calculate VDS
1. Transistor is saturated.
using the output loop
2. IG=IB=0.
 Bias Analysis 1- Constant GS Voltage Biasing (1)

The left (input) loop. Since IG=0:

V I R V  0 V V  3V
EQ G EQ GS GS EQ

Then, from the transistor equation:

Kn  
2
I  V V 
D 2  GS TN 
 2510  6 
 
  A
   3 12 V2  50 A

2 V2
 Bias Analysis 1- Constant GS Voltage Biasing (1)
The right (output) loop:
V  I R V 0
DD D D DS

V  10V  (50uA)(100K )  5.00 V

DS

Check:VDS>VGS-VTN. Hence saturation

The left (input) loop. Since IG=0: region assumption is correct.
V I R V  0 V V  3V Q-pt: (50.0 mA, 5.0 V) with VGS= 3.0V
EQ G EQ GS GS EQ
Discussion.
Then, from the transistor equation:
The obtained result is proportional to K and
Kn  
2 to the square of VTN , thus Q-pt. is quite
I  V V 
D 2  GS TN  sensitive to the parameter fluctuation of the
 2510  6 
  device, so this circuit is not very used.
  A
   3 12 V2  50 A

2 V2
Bias Analysis 1- Constant GS Voltage Biasing (2)
Now let’s repeat the same problem taking
into account channel length modulation.
K  2 
I  n V V  1 V 

D 2  GS TN   DS 
V V I R
DS DD D D
(25106 ) 210.02 V 
V 10V (100K)
DS   
31
DS

2 
 4.55 V
(25106 )
I  312 10.02 (4.55) 54.5 A
D 2

Check:VDS>VGS-VTN. Hence
saturation region assumption is
correct.
Q-pt: (54.5 mA, 4.55 V) with
VGS= 3.00 V
Bias Analysis 1- Constant GS Voltage Biasing (2)
Now let’s repeat the same problem taking
into account channel length modulation.
K  2 
I  n V V  1 V 

D 2  GS TN   DS 
V V I R
DS DD D D
(25106 ) 210.02 V 
V 10V (100K)
DS   
31
DS

2 
 4.55 V
(25106 )
I  312 10.02 (4.55) 54.5 A
D 2
Discussion.
Check:VDS>VGS-VTN. Hence
saturation region assumption is The bias levels have changed by
correct. about 10%. Typically, component
values will vary more than this, so
Q-pt: (54.5 mA, 4.55 V) with there is little value in including 
VGS= 3.00 V effects in most circuits.
Bias Analysis 1- Constant GS Voltage Biasing (3)
Load Line Analysis.

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the
load line. Use this to find Q-pt at
intersection of load line with device
characteristic.
Assumptions:
1. IG=IB=0.
Do we need assumption for the
transistor region of operation?
Bias Analysis 1- Constant GS Voltage Biasing (3)
Load Line Analysis.

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the
load line. Use this to find Q-pt at
intersection of load line with device
characteristic.
Assumptions:
1. IG=IB=0.
2. No need for region assumption,
will find solution directly.
Bias Analysis 1- Constant GS Voltage Biasing (3)
Load Line Analysis.

Problem: Find Q-pt (ID, VDS , VGS)

Analysis: First, simplify circuit with
Approach: Find an equation for the Thevenin transformation to find VEQ
load line. Use this to find Q-pt at and REQ for gate-bias voltage
intersection of load line with device
characteristic.
Assumptions:
1. IG=IB=0.
2. No need for region assumption,
will find solution directly.
Bias Analysis 1- Constant GS Voltage Biasing (3)
Load Line Analysis.

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the
load line. Use this to find Q-pt at
intersection of load line with device
characteristic.
Assumptions:
1. IG=IB=0.
Analysis: First, simplify circuit with
Thevenin transformation to find VEQ
and REQ for gate-bias voltage
The left (input) loop. Since IG=0:
V I R
EQ G EQ GS
V 0 

2. No need for region assumption, V V  3V

GS EQ
will find solution directly.
 Bias Analysis 1- Constant GS Voltage Biasing (3)
Load Line Analysis.

From the KVL for the right loop, load

line becomes
V  I R V
DD D D DS
10  I 100K V Check: The load line approach agrees with
D DS previous calculation.

Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V
@VDS=0, ID=100uA, @ID=0, VDS=10V
 Discussion: Q-pt is clearly in the saturation
Plotting on device characteristic yields region. Graphical load line is good visual
Q-pt at intersection with VGS = 3V aid to see device operating region.
device curve.
Bias Analysis 2 - Four-Resistor Biasing (1)

Analysis: First, simplify circuit, split

VDD into two equal-valued sources and
apply Thevenin transformation to find
VEQ and REQ for gate-bias voltage

Problem: Find Q-pt (ID, VDS)

Approach: Assume operation region,
find Q-point, check to see if result is
consistent with operation region
Assumption: Transistor is saturated,
IG=IB=0
 Bias Analysis 2 - Four-Resistor Biasing (1)

Left loop. Since IG=0,

VEQ  VGS  I D RS  0
Kn
VEQ  VGS  VGS  VTN 2 RS
2
25106 3.910 4 
  

   2

4 V    
 V 1
GS 2

 GS 

 V 2 0.05V  7.21 0
GS GS


 Bias Analysis 2 - Four-Resistor Biasing (1)
Solution: V  2.71V,  2.66V
GS
If VGS= -2.71 , VGS<VTN and
MOSFET will be cut-off. Thus
V 2.66V
GS and ID= 34.4 mA



Left loop. Since IG=0,

VEQ  VGS  I D RS  0
Kn
VEQ  VGS  VGS  VTN 2 RS
2
25106 3.910 4 
  

   2

4 V    
 V 1
GS 2

 GS 

 V 2 0.05V  7.21 0
GS GS


 Bias Analysis 2 - Four-Resistor Biasing (1)
Solution: V  2.71V,  2.66V
GS
If VGS= -2.71 , VGS<VTN and
MOSFET will be cut-off. Thus
V 2.66V
GS and ID= 34.4 mA

 Right loop.
Left loop. Since IG=0, V  I (R  R )  V 0 
DD D D S DS
VEQ  VGS  I D RS  0
V  6.08V
K DS
VEQ  VGS  n VGS  VTN 2 RS
2
25106 3.910 4 
   We have VDS >VGS-VTN .
   2
4 V    
 V 1 Hence saturation region assumption is
GS 2

 GS 
correct.
 V 2 0.05V  7.21 0 Q-pt: (34.4 mA, 6.08 V) with
GS GS
VGS= 2.66 V

 Bias Analysis 2 - Four-Resistor Biasing (2)
Body Effect
In previous example, the body terminal V V   ( V 2  2 )
TN TO SB F F
was connected to the source, so VSB = 0.
Now let’s consider the case with VSB  0 V 10.5( V 0.6  0.6)
 TN SB

6 
2510 

2
 

I ' 
V V 
D 2

 GS TN 

 Iterative solution can be found by

following steps:

• Estimate value of ID and use it to

find VGS and VSB
• Use VSB to calculate VTN
V V  I R  622,000I • Find ID’ using last equation
GS EQ D S D
• If ID’ is not same as original ID
V  I R  22,000I estimate, start again.
 SB D S D


 Bias Analysis 2 - Four-Resistor Biasing (2)
Body Effect

The iteration sequence leads to ID= 88.0 mA, VTN = 1.41 V,

V V  I (R R )10 40,000I  6.48V
DS DD D D S D

 We obtained that VDS>VGS-VTN. Hence saturation region assumption is

correct.
Q-pt: (88.0 mA, 6.48 V)
Check: VDS > VGS - VTN, therefore still in active region.
Discussion: Body effect has decreased current by 12% and increased
threshold voltage by 40%.
 Bias Analysis 3 – Two Resistor (saturation)

Assumption:
1. IG=IB=0.
2.Transistor is saturated since VDS=VGS
 Bias Analysis 3 – Two Resistor (saturation)

Assumption:
1. IG=IB=0.
2.Transistor is saturated since VDS=VGS
Analysis. No need for input loop: VDS=VGS
V V I R
Output loop: DS DD D D


 Bias Analysis 3 – Two Resistor (saturation)
K 2
V V V  n V V  RD
GS DS DD 2  GS TN 

 2.6 10  4 10 4 

  
   2
V  3.3     V 1
GS 2

 GS 

V  0.769V,  2.00V
GS

If VGS= -0.769 , VGS<VTN and

Assumption:
1. IG=IB=0. MOSFET will be cut-off. Thus
2.Transistor is saturated since VDS=VGS V V  2.00V and ID= 130 mA
GS DS
Analysis. No need for input loop: VDS=VGS We obtained VDS>VGS-VTN. Hence
V V I R saturation region assumption is
Output loop: DS DD D D
correct.

Q-pt: (130 mA, 2.00 V)
Discussion of Four and Two-Resistor Biasing
Four resistor
• Provide excellent bias for transistors in discrete circuits.
• Stabilize bias point with respect to device parameter and temperature
variations using negative feedback.
• Use single voltage source to supply both gate-bias voltage and drain
current.
• Generally used to bias transistors in saturation region in amplifier circuits.
Two-resistor
• Uses lesser components that four-resistor biasing and also isolates drain
and gate terminals.

• Feedback mechanism.
Suppose, for some reason ID begins to increase. From VEQ  VGS  I D RS  0 it follows
that VGS has to decrease, since Vg is constant. This will decrease the current ID due to
current equation, thus restoring the existing state.
 Bias Analysis 4 – One Resistor (triode)

Assumption:
1. IG=IB=0
2. Transistor is saturated.
Analysis.
Left loop: VGS=VDD=4 V

I  250 A (41)2 1.13mA

D 2 V2


 Bias Analysis 4 – One Resistor (triode)
Right loop: V  I R V
DD D D DS
V  41600I
DS D
V  2.19V
DS

Assumption:
1. IG=IB=0
2. Transistor is saturated.
Analysis.
Left loop: VGS=VDD=4 V

I  250 A (41)2 1.13mA

D 2 V2
 Bias Analysis 4 – One Resistor (triode)
Right loop: V  I R V
DD D D DS
V  41600I
DS D
V  2.19V
DS
We obtained VDS<VGS -VTN. Hence,
saturation region assumption is incorrect.

Assume the triode region and use the

Assumption: triode region equation:
A VDS
1. IG=IB=0 VDS  4  1600  250 2
(4  1  )VDS
V 2
2. Transistor is saturated.
Analysis. VDS  2.3, 8.7 = 2.3V and ID=1.06 mA
Left loop: VGS=VDD=4 V We obtained VDS<VGS -VTN, transistor is in
triode region
I  250 A (41)2 1.13mA
D 2 V2 Q-pt:(1.06 mA, 2.3 V)
 Bias Analysis 5 - Two-Resistor, PMOST
Right loop: 15V  (220k) I D VDS  0

2
15V  (220k) 50  A V  2  V  0
2 V2  GS  GS

V  0.369V, 3.45V
GS

Since VGS= -0.369 V is more than VTP= -2 V,

we take VGS = -3.45 V
Assumption:
1. IG=IB=0 Then we can calculate ID = 52.5 mA.

2. Transistor is saturated: VDS=VGS Check: VDS  VGS VTP

Hence saturation assumption is correct.
Analysis. 
Q-pt: (52.5 mA, -3.45 V)
Left loop: no need, VDS=VGS
Junction Field-Effect
Transistors (JFET)
 Junction Field-Effect
Transistors (JFET)
• MOSFET devices are called FET because electric field is used to control the shape and
hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor
device.
• There is another type of FET, which is not using MOS capacitor structure, however utilizes
the electric filed effect: Junction Field-Effect Transistor.
• Less prevalent than MOSFET, JFET have many uses, especially in analog RF applications.
• Can be of two types: n-channel and p-channel JFET.

n-channel JFET consists of:

• n-type semiconductor block that houses
the channel region in n-channel JFET.
• pn junction - forms the gate.
• Source and drain terminals

Like a diode with enlarged n-type section and two n-terminals.

 JFET Structure
• With no bias applied, a resistive channel
exists. The current enters channel at the
drain and exits at source.

• The resistance of the drain-source

channel is controlled by changing the
physical width of the channel through
modulation of the depletion layers
around pn-junctions (like squeezing a
• In triode region, JFET is a voltage-
garden hose)
controlled resistor,
RCH  t L
W
• Application of reverse bias to the gate-
r - resistivity of channel
channel diodes causes the depletion
L - channel length layer to widen, reducing the channel
W - channel width between pn junction width and decreasing the current.
depletion regions
t - channel depth • JFET is inherently a depletion-mode
device – a voltage must be applied to
turn the device off.
JFET: applying Gate-Source voltage

• vGS = 0. The channel width is W. It can

conduct current well if vDS is applied.
JFET: applying Gate-Source voltage

• vGS = 0. The channel width is W. It can

conduct current well if vDS is applied.

• VP < vGS <0. The depletion layers width is

increased. The channel width W’ < W,
and channel resistance increases. Gate-
source junction is reverse-biased, iG
almost 0.
JFET: applying Gate-Source voltage

• vGS = 0. The channel width is W. It can

conduct current well if vDS is applied.

• VP < vGS <0. The depletion layers width is

increased. The channel width W’ < W,
and channel resistance increases. Gate-
source junction is reverse-biased, iG
almost 0.

• vGS = VP < 0. The depletion layer is max.

Channel width – zero, region is pinched-
off, channel resistance is infinite.
JFET: applying Drain-Source voltage
• With constant vGS, depletion region near
drain increases with vDS
JFET: applying Drain-Source voltage
• With constant vGS, depletion region near
drain increases with vDS

• At vDSP = vGS - VP , channel is totally

pinched-off; iD is saturated. (the current
does not stop: electrons are accelerated down the
channel (V is large), are injected into the depletion
region and swept to the drain)
JFET: applying Drain-Source voltage
• With constant vGS, depletion region near
drain increases with vDS

• At vDSP = vGS - VP , channel is totally

pinched-off; iD is saturated. (the current
does not stop: electrons are accelerated down the
channel (V is large), are injected into the depletion
region and swept to the drain)

• JFET also suffers from channel-length

modulation like MOSFET at larger
values of vDS.
JFET: applying Drain-Source voltage
• With constant vGS, depletion region near
drain increases with vDS

• At vDSP = vGS - VP , channel is totally

pinched-off; iD is saturated. (the current
does not stop: electrons are accelerated down the
channel (V is large), are injected into the depletion
region and swept to the drain)

• JFET also suffers from channel-length

modulation like MOSFET at larger
values of vDS.
 N-Channel JFET i-v Characteristics
The JFET iv-characteristics are remarkably similar to the MOSFET characteristics
(virtually identical).

Transfer Characteristics Output Characteristics

 N-Channel JFET i-v equations
Equations are similar to MOSFET except written slightly differently
• For all regions : iG  0 for vGS  0
• In cutoff region: iD  0 for vGS VP VP  0
• In Triode region: 
 2
2I DSS  vDS 
iD  v
 GS VP  
 vDS for vGS  VP and vGS VP  VDS  0
VP 2  2 

• In pinch-off region:
2
 v 
iD  I 1 GS

DSS 
 VP



1vDS  for vGS  VP and vDS  vGS VP  0
 
Explanation:
2 2
Kn Kn  v   vGS 
iD  (vGS VP )  (VP ) 1 GS
2 2 
 = I DSS  1  ,
2 2 
 VP 


 VP 

Kn
where I  (VP )2 , I [10μA, 10A], VP [25V, 0]
DSS 2 DSS

Typically: I DSS [10 A, 10 A], VP [-25V, 0V]

 P-Channel JFET

• Polarities of n- and p-type regions of the n-channel

JFET are reversed to get the p-channel JFET.
• Channel current direction and operating bias voltages
are also reversed.
 JFET Circuit Symbols

n-channel p-channel

• JFET structures are symmetric like MOSFETs.

• Source and drain determined by circuit voltages.
JFET n-Channel Model Summary
JFET p-Channel Model Summary
 Biasing JFET (1)

N-channel JFET Depletion-mode MOSFET

Kn 400 A/V 2
I  (VP ) 
2 (5)2  5000 A  5mA
DSS 2 2

• Assumptions: Gate-channel junction is reverse-biased, reverse leakage

current of gate, IG = 0
Biasing JFET (2) DIY
 Biasing JFET (3)
Region Assumption: JFET is pinched-off (saturation)

Input loop: IG  0, I S  I D  VGS   I D RS

2 2
 V   V 
VGS   I DSS RS 1 GS
 VP


   5103 A 
 
1000  1 GS 

5V 
  
VGS  1.91V, 13.1V

Since VGS = -13.1 V is less than VP= -5 V , we take VGS = -1.91 V (n-channel type!)
and, ID = IS = 1.91 mA.
Output loop: VDS VDD  ID(RD  RS )12(1.91mA)(3k) 6.27V

VDS >VGS-VP. Hence pinch-off region assumption is correct and gate-

source junction is reverse-biased by 1.91V.
Q-pt: (1.91 mA, 6.27 V)
Internal Capacitances in Electronic Devices

• Limit high-frequency performance of the electronic device

they are associated with.

• Limit switching speed of circuits in logic applications

• Limit frequency at which useful amplification can be

obtained in amplifiers.

• MOSFET capacitances depend on operation region and are

non-linear functions of voltages at device terminals.
 NMOS Transistor Capacitances: Triode Region

Cox” =Gate-channel capacitance

per unit area(F/m2).
CGC =Total gate channel
capacitance.
CGS = Gate-source capacitance.
C
C  GC C W Cox"WL C W CGD =Gate-drain capacitance.
GS 2 GSO 2 GSO
C CGSO and CGDO = overlap

C  GC C W Cox"WL C W
GD 2 GSO 2 GSO capacitances (F/m).
 CSB = Source-bulk capacitance.
C C A C P CDB = Drain-bulk capacitance.
SB J S JSW S
AS and AD = Junction bottom area

C C A C P capacitance of the source and drain
DB J D JSW D
regions.
 PS and PD = Perimeter of the source and
drain junction regions.
NMOS Transistor Capacitances: Saturation Region

• Drain no longer connected to channel

C  2 C C W
GS 3 GC GSO
C C W
 GD GDO


NMOS Transistor Capacitances: Cutoff Region

• Conducting channel
region completely
gone.

C C W CGB = Gate-bulk
GS GSO
capacitance
C C W CGBO = gate-bulk

GD GDO
C C W capacitance per unit

GB GBO
width.

JFET Capacitances

• CGD and CGS are determined by depletion-

layer capacitances of reverse-biased pn
junctions forming gate and are bias
dependent.
SPICE Model for NMOS Transistor
Typical default values used by SPICE:
Kn or Kp = 20 mA/V2
g=0
l=0
VTO = 1 V
mn or mp = 600 cm2/V.s
2FF = 0.6 V
CGDO=CGSO=CGBO=CJSW= 0
Tox= 100 nm
SPICE Model for JFET

• Typical default values used by SPICE:

Vp = -2 V
l = CGD = CGD = 0
Transconductance parameter BETA
BETA = IDSS/VP2 = 100 mA/V2