8051 Micro controller Diagram

RAM ROM I/O PORTS

CPU

TIMERS/ SERIAL
INTERRUPTS
COUNTERS PORT
CPU- Central processing Unit

Bit capacity - 8 bit

Architecture - Harvard
Address bus - 16bit-64k
CPU Data bus - 8bit- 256
Registers - A,B,
R0,R1,R2,R3,R4,R5,R6,R7
DPTR, PC
 RAM- Random Access Memory:
7fh 1 Byte (0 to 255)

128 bytes

0 to 127

00h to 7fh

Read /Write memory

00h
Data memory
 ROM: Read Only Memory
1 Byte(0 to 255)
0fffh

4k bytes

0 to 4095

0000h to 0fffh

Read only memory

Code/ program memory

0000h
 I/O PORTS- Input/output Ports:
Used to connect
4 I/O Ports- 32 Pins

PORT 0 – P0.7 to P0.0

PORT 1 - P1.7 to P1.0

PORT 2 – P2.7 to P2.0

PORT3 - P3.7 to P3.0

 TIMERS/ COUNTERS:

2- 16 bit Timers/ Counters

T0 & T1

Generate Accurate Time delays

Count External pulses

 INTERRUPTS: Main Program

6 Interrupt sources including

reset
3- Hardware interrupts Interrupt

Reset
INT0
INT1
3 –Software interrupts
Timer0 Interrupt service routine-ISR

Timer1
serial TI/RI
 SERIAL PORT: Used to communicate
1 Serial protocol

UART – Universal
Asynchronous
Receiver / Transmitter
RXD
TXD pins
Thank you.