ELECTRICAL

VALIDATION FOR
DDR IO INTERFACE
Under the Guidance
of
Prof. M. S. Bhat Bhide Amruta A
NITK Surathkal Intel Technology India Pvt. Ltd.

Presented by
Dipak Prakash Bankar
09VL07F

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 Agenda :
What is EV In general?
Importance.
What is DDR Interface?
Brief About DDR RAM.
Evolution Of DDR.
DDR3 Signals.
DDR3 protocol.
EV for DDR.
Flyby Topology.
Delay Locked Loop
Characterization of DLL.
References.
12/09/21 M. Tech. VLSI Design NITK Surathkal. 2
What is EV in general?
• It comes under post silicon Validation.
• Done over Process, Voltage and Temperature
variations.
• Done at
» Platform Level
» Component Level

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Importance.

12/09/21 M. Tech. VLSI Design NITK Surathkal. 4

What is DDR interface? SATA/
USB/
PCIe/AG Other LAN
P(Graphic Devices HDMIPORTS
s)

DDR Interface

APM/ PCI/P AC97/HD

Memory Slots
ACPI CIe (AUDIO)
Bus

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 What is DDR interface? SATA/
USB/
PCIe/AG
P(Graphic Other LAN
s) Devices HDMIPORTS

Two Die
one package

DDR Interface

APM/ PCI/P AC97/HD

DDR ACPI CIe (AUDIO)
Slots Bus

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 What is DDR interface?
PCIe/AG
VGA HDMI P(Graphic
s)

Other
APM/
Devices
ACPI
PCI/P SATA/
CIe USB/
Bus LAN
PORTS
DDR Interface

DDR Slots

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Brief about DDR(RAM).
• Evolution of DDR.
• DDR3 Signals.
• DDR3 protocol.
– READ
– WRITE

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 Evolution of DDR.
• Evolved from SDR

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 Evolution of DDR.
• DDR1.

Additional
Stubs and Stub
Lengths

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  Evolution of DDR.
• DDR2.

Additional
Stubs and Stub
Lengths

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 Evolution of DDR.
• DDR3.

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DDR3 Signals Groups.
• Command group
 WE# : Write Enable
 RAS# : Row Address Select
 CAS# : Column Address Select

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DDR3 Signals Groups.
• Clock
 CK/CK# :
- Differential.
- Free running.
- all data, address, command and control signals are sampled on the
crossing of clock.

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DDR3 Signals Groups.
• Control group
 CKE : Clock Enable
- Activate and deactivate internal clock signals and device input buffers and
output drivers.
- CKE LOW provides Pre-charge Power-Down and Self
Refresh operation.

 CS : Chip Select
- CS provides for external
Rank selection on systems with multiple Ranks.
- All commands are masked when CS is registered HIGH.

 ODT : On Die Termination

- ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM.
- Allows the DRAM to turn on/off termination resistance for each DQ,
DQS, DQS#.

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DDR3 Signals Groups.
• Data group
 DQS/DQS# [7:0] : Data Strobe
- Differential.
- Acts as clock for data.
- Starts from Tristate.

 DQ[63:0]
- Single ended Bi-directional.
- Center aligned w.r.t. DQS during write.
- Edge aligned w.r.t. DQS during read.
- 1 DQS is associated with each 8-bit data(DQ)

 DM[7:0] : Write Data Mask

- 1 for each 8-bit data (DQ).

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DDR3 Protocol.
• WRITE
• READ

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DDR3 Protocol.
• WRITE

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DDR3 Protocol.
• READ

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 EV For DDR.
• Platform Level - Signal Integrity
 Addresses two concerns in the electrical design aspects
- the timing and
- the quality of the signal

 The goal of signal integrity analysis is to ensure reliable high-speed data

transmission.

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 EV For DDR.
• Platform Level - Signal Integrity
 Main issues of SI

• Reflection Noise
• Due to impedance mismatch, stubs, vias and other interconnect
discontinuities.

• Crosstalk Noise
• Due to electromagnetic coupling between signal traces and vias.

• Power/Ground Noise
• Due to paracitic of the power/ground delivery system during drivers’
simultaneous switching output (SSO). It is sometimes also called
Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).

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EV for DDR.
• Platform Level - Signal Integrity
1. Clk to DQS Skew

2. Clk VIX

3. Clock Jitter characterization

4. Dq-Dqs timing

5. Clk-Control timing

6. Clk-Command timing

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EV for DDR.
• Platform Level - Signal Integrity
1. Clk to DQS Skew

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EV for DDR.
• Platform Level - Signal Integrity
2. Clk VIX

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EV for DDR.
• Platform Level - Signal Integrity
2. Clk VIX

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EV for DDR.
• Platform Level - Signal Integrity
4. Dq-Dqs timing

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EV for DDR.
• Platform Level - Signal Integrity
5. Clk-Control(CS#) timing

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EV for DDR.
• Platform Level - Signal Integrity
6. Clk-Command (WE#) timing

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EV for DDR.
• Component Level
 Characterization Of AC timings
- Slew Rate
- Duty Cycle
- Noise Margins
- Set up and Hold check

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 EV For DDR.
Process Temperature Voltage
(˚C) (V)
Board Component (Processor)

LOW-Z Slow Low Low

High-Z Fast High High

Typical typical Typical Typical

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Flyby topology.
Flyby topology.
• Clock gets skewed

• DQS should be skewed accordingly

• Uses programmable Delay element

known as Delay Locked Loop(DLL).
Delay Locked Loop(DLL)

Phase Fast/Slow
Clk in Detector Control

Delay Line

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Characterization of DLL(My
Work).
• Code Vs Delay
Characterization of DLL.
• DNL
Characterization of DLL.
• INL
References
•JEDEC
•www.csee.umbc.edu/research/vlsi/reports/si_chapter.pdf
•“Clocking in Modern VLSI System” by Thucydides Xanthopoulos, Spinger.
•Intel Internal Reference Documents

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