ECEN720: High-Speed Links

Circuits and Systems

Spring 2021

Lecture 11: Clocking Architectures & PLLs

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Lab 5 Report and Prelab 6 due Mar. 31

2
Agenda
• Clocking Architectures

• PLLs
• Modeling
• Noise transfer functions

3
References
• High-speed link clocking tutorial paper, PLL
analysis paper, and PLL thesis posted on
website
• Posted PLL models in project section
• Website has additional links on PLL and
jitter tutorials
• Majority of today’s PLL material comes
from Fischette tutorial and M. Mansuri’s
PhD thesis (UCLA)
4
High-Speed Electrical Link System

5
Clocking Terminology
Synchronous
• Every chip gets same frequency AND phase
• Used in low-speed busses

Mesochronous
• Same frequency, but unknown phase
• Requires phase recovery circuitry
• Can do with or without full CDR
• Used in fast memories, internal system interfaces,
MAC/Packet interfaces
Plesiochronous
• Almost the same frequency, resulting in slowly
drifting phase
• Requires CDR
• Widely used in high-speed links

Asynchronous
• No clocks at all
• Request/acknowledge handshake procedure
• Used in embeddded systems, Unix, Linux
[Poulton] 6
I/O Clocking Architectures
• Three basic I/O architectures
• Common Clock (Synchronous)
• Forward Clock (Source Synchronous)
• Embedded Clock (Clock Recovery)

• These I/O architectures are used for varying applications

that require different levels of I/O bandwidth

• A processor may have one or all of these I/O types

• Often the same circuitry can be used to emulate different

I/O schemes for design reuse

7
Common Clock I/O Architecture

[Krauter]

• Common in original computer systems

• Synchronous system by design (no active deskew)
• Common bus clock controls chip-to-chip transfers
• Requires equal length routes to chips to minimize clock skew
• Data rates typically limited to ~100Mb/s 8
Common Clock I/O Cycle Time

[Krauter]

9
Common Clock I/O Limitations
• Difficult to control clock skew and propagation delay
• Need to have tight control of absolute delay to meet a given
cycle time
• Sensitive to delay variations in on-chip circuits and board
routes
• Hard to compensate for delay variations due to low
correlation between on-chip and off-chip delays
• While commonly used in on-chip communication, offers
limited speed in I/O applications

10
Forward Clock I/O Architecture
• Common high-speed reference
clock is forwarded from TX chip
to RX chip
• Mesochronous system
• Used in processor-memory
interfaces and multi-processor
communication
• Intel QPI
• Hypertransport
• Requires one extra clock
channel
• “Coherent” clocking allows low-
to-high frequency jitter
tracking
• Need good clock receive
amplifier as the forwarded clock
is attenuated by the channel 11
Forward Clock I/O Limitations
• Clock skew can limited forward
clock I/O performance
• Driver strength and loading
mismatches
• Interconnect length
mismatches

• Low pass channel causes jitter

amplification

• Duty-Cycle variations of
forwarded clock

12
Forward Clock I/O De-Skew
• Per-channel de-skew allows for
significant data rate increases
• Sample clock adjusted to center
clock on the incoming data eye
• Implementations
• Delay-Locked Loop and Phase
Interpolators
• Injection-Locked Oscillators

• Phase Acquisition can be

• BER based – no additional
input phase samplers
• Phase detector based
implemented with additional
input phase samplers
periodically powered on
13
Forward Clock I/O Circuits
• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit
• DLL/PI
• Injection-Locked Oscillator

14
Embedded Clock I/O Architecture
• Can be used in mesochronous
or plesiochronous systems

• Clock frequency and optimum

phase position are extracted
from incoming data stream

• Phase detection continuously

running

• CDR Implementations
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator
PLLs 15
Embedded Clock I/O Limitations
• Jitter tracking limited by
CDR bandwidth
• Technology scaling allows
CDRs with higher
bandwidths which can
achieve higher frequency
jitter tracking

• Generally more hardware

than forward clock
implementations
• Extra input phase
samplers

16
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

17
Xilinx 0.5-32Gb/s Transceiver Clocking
Channels 1-4
Frac-N LC PLL1, 2 Technology CMOS 16nm FinFET
Power Supply (Vavcc, Vavtt, Vaux) 0.9 V, 1. 2V, 1.8 V
∑ Transmitter Frequency range 500 Mb/s – 32.75 Gb/s
DCC Transceiver Quad area 2.625 mm × 2.218 mm
VCOLB LC PLL range 8-16.375 GHz
Ring PLL range 2-6.25 GHz
VCOHB Receiver
TX PRBS7 jitter at 32.75Gb/s TJ: 5.39 ps, RJ: 190 fs
PI (D,X,S) 32.75Gb/s RX JTOL @ 30MHz 0.45 UI
PPF 2 IQ CAL @ 100MHz 0.6 UI
Channel loss at 32.75Gb/s 30 dB
DCC < 10-15
Measured BER at 32.75Gb/s
Ring PLL Power at 32.75Gb/s with DFE 577mW/ch (17.6pJ/b)

I/Q1, I/Q2
Active Inductor based Clock Distribution
[Upadhyaya VLSI 2016]

• LC-PLL with 2 LC-VCOs used to cover high data rates

(8-32Gb/s)
• Ring-PLL used for lower data rates
• CML clock distribution with active inductive loads used
for low jitter
18
PLLs
• PLL modeling

• PLL noise transfer functions

19
PLL Block Diagram

[Perrott]

• A phase-locked loop (PLL) is a negative feedback system

where an oscillator-generated signal is phase AND
frequency locked to a reference signal

20
PLL Applications
• PLLs applications
• Frequency synthesis
• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation
• Phase aligning an internal clock to an I/O clock
• Clock recovery
• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation
• Wireless systems
• Spread-spectrum clocking

21
Forward Clock I/O Circuits
• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit
• DLL/PI
• Injection-Locked Oscillator

22
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

23
 PLL Design Challenges
• Board-level reference clock frequencies don’t scale often
• 156MHz is a common frequency
• RX CDR bandwidth is hard to scale with PAM4 signaling and
ADC-based front-ends
• Typically 2-4MHz
• PLL bandwidth must be kept less than 10MHz for stability
and to filter reference jitter
• VCO phase noise at low-frequency offsets due to flicker
noise must be suppressed
32.75Gbps Transceiver PLL Simulated Jitter Numbers
Receiver Type PLL PN @1MHz CDR BW RJ RJ in UI
Analog based RX -92.4dBc/Hz 12.7MHz 160.7fs 5.26mUI
ADC based RX -92.4dBc/Hz 2MHz 407fs 13.3mUI

[Turker ISSCC 2019] 24

Charge Pump PLL
PFD
D UP
Q ICP
in R

Vctrl VCO out

R DN
fb Q R C2
D
ICP
C1

Divider

1/N

• Charge pump PLL is a common implementation

• Type-2 (2 integrators) allows for ideally zero phase error between
the input and feedback phase
• Requires a stabilizing zero that is realized with the filter resistor
• A secondary capacitor C2 is often added for additional filtering to
reduce reference spurs
• Modeled as a third-order system 25
Linear PLL Model
Phase Detector
Loop Filter VCO

e KVCO
in  F(s) Vctrl out
KPD s

fb
1
N
Divider

For Charge Pump PLL: 𝐾PD = 𝐼 CP

2𝜋
1
𝐶2 1
𝑠 + 𝑅𝐶 1
𝐹 𝑠 =
𝐶1 + 𝐶2
𝑠 𝑠 + 𝑅𝐶 𝐶
1 2

𝐾 PD𝐾 VCO 1
𝐶2 𝑠 + 𝑅𝐶
𝐻 𝑠 = 𝜙out 𝑠 = 𝐶1 + 𝐶2
1
𝐾 PD𝐾 VCO
𝜙 in 𝑠 𝑠3 + 𝑅𝐶1𝐶2 𝑠 + 𝐾 PD𝐾 VCO
2
𝑁𝐶2 𝑠 + 𝑁𝑅𝐶 𝐶
1 2
26
 Understanding PLL Frequency Response
• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain operation in
lock range
• Frequency domain analysis can tell us how well the PLL tracks the input
phase as it changes at a certain frequency
• PLL transfer function is different depending on which point in the loop
the output is responding to
Input phase response VCO output
response

[Fischette]
27
Input Noise Transfer Function
Phase Detector
Loop Filter VCO

e K VCO
n,in  F(s) Vctrl out
K PD s

fb
1
N
Divider

𝐾 PD𝐾 VCO 1
𝜙out 𝑠 𝐶2 𝑠 + 𝑅𝐶 1
Input Phase Noise: 𝐻n I N 𝑠 = 𝑠 = 3 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
𝑠 + 𝐾 PD𝐾 VCO
𝑅𝐶1𝐶2 𝑠 +
𝜙n I N 2
𝑁𝐶2 𝑠 + 𝑁𝑅𝐶 𝐶
1 2

28
Input Noise Transfer Function
Parameter
Fref 156MHz
N 90
Fvco 14GHz
Icp 100uA
R 22.7k
C1 7.0pF
C2 500fF
Kvco 2π*1GHz/V
5.9MHz
f3dB
60°
Phase Margin

𝐾 PD𝐾 VCO 1
𝜙out 𝑠 𝐶2 𝑠 + 𝑅𝐶 1
Input Phase Noise: 𝐻n I N 𝑠 = 𝑠 = 3 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
𝑠 + 𝐾 PD𝐾 VCO
𝑅𝐶1𝐶2 𝑠 +
𝜙n I N 2
𝑁𝐶2 𝑠 + 𝑁𝑅𝐶 𝐶
1 2

29
VCO Noise Transfer Function
Phase Detector
Loop Filter VCO
vn,vco n,vco
e KVCO
in  F(s) Vctrl   out
KPD s

fb
1
N
KVCO is different if the input is at the
Divider
Vcntrl input (KVCO) or supply (KVdd)

𝐶1 + 𝐶2
𝑠2 𝑠 +
VCO Phase Noise: 𝐻n 𝑠 = 𝜙 out 𝑠 = 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
7C0 𝑠
𝑠 + 𝑅𝐶1𝐶2 𝑠 +𝑅𝐶1𝐶2𝑁𝐶2 𝐾 PD𝐾 VCO
𝜙n 7 C 0 3 2
𝑠 + 𝑁𝑅𝐶 𝐶
1 2

𝐶1 + 𝐶2
𝐾VCO 𝑠 𝑠 +
Voltage Noise on 𝜙 out 𝑠 𝑅𝐶1 𝐶2
𝑇 𝑠 = = 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
VCO Inputs: n 7C0 𝑠
𝑠 + 𝐾 PD𝐾 VCO
𝑅𝐶1𝐶2 𝑠 +
𝑣n 7 C 0 3 2
𝑁𝐶2 𝑠 + 𝑁𝑅𝐶 𝐶
1 2

30
VCO Noise Transfer Function
Parameter
Fref 156MHz
N 90
Fvco 14GHz
Icp 100uA
R 22.7k
C1 7.0pF
C2 500fF
Kvco 2π*1GHz/V
5.9MHz
f3dB
60°
Phase Margin

𝐶1 + 𝐶2
𝑠2 𝑠 +
VCO Phase Noise: 𝐻n 𝑠 = 𝜙 out 𝑠 = 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
7C0 𝑠
𝑠 + 𝑅𝐶1𝐶2 𝑠 +𝑅𝐶1𝐶2𝑁𝐶2 𝐾 PD𝐾 VCO
𝜙n 7 C 0 3 2
𝑠 + 𝑁𝑅𝐶 𝐶
1 2

𝐶1 + 𝐶2
𝐾VCO 𝑠 𝑠 +
Voltage Noise on 𝜙 out 𝑠
𝑅𝐶1 𝐶2
𝑇 𝑠 = = 𝐶1 + 𝐶2 𝐾 PD𝐾 VCO
VCO Inputs: n7C0 𝑠
𝑠 + 𝐾 PD𝐾 VCO
𝑅𝐶1𝐶2 𝑠 +
𝑣n 7 C 0 3 2
𝑁𝐶2 𝑠 + 𝑁𝑅𝐶 𝐶
1 2 31
 28GHz PLL Phase Noise Example
Phase Noise (dBc/Hz)

With ~100fs target,

no single dominant source -
every component contributes

Frequency Offset (Hz) [Turker ISSCC 2019]

• Charge pump noise dominates at low frequencies

• VCO noise at mid-band and high frequencies
• Output buffers outside loop dominate at high frequencies
32
PLL Noise Transfer Function Take-Away
Points

• The way a PLL shapes phase noise depends

on where the noise is introduced in the
loop
• Optimizing the loop bandwidth for one noise
source may enhance other noise sources
• Generally, the PLL low-pass shapes input
phase noise, band-pass shapes VCO input
voltage noise, and high-pass shapes
VCO/clock buffer output phase noise 33
 Oscillator Noise
Jitter

[McNeill] 34
Oscillator Phase Noise Model

[Perrott]

 Noise Spectral Density 

L f   10 log dBc/Hz 
Carrier Power 
  f

2

Leeson’s Model: Lf  
 10  2FkT  1  1 f o  1 1/ f 3

P f 
log  sig   2Q f   
• For improved model see Hajimiri papers
35
Open-Loop VCO Jitter
[McNeill]

T

• Measure distribution of clock threshold crossings

• Plot  as a function of delay T
36
Open-Loop VCO Jitter
[McNeill]

 T OL T    T

• Jitter  is proportional to sqrt(T)

•  is VCO time domain figure of merit
37
 VCO in Closed-Loop PLL Jitter

[McNeill]

• PLL limits  for delays longer than loop bandwidth L

 L  1 2fL
38
 Ref Clk-Referenced vs Self-Referenced
[McNeill] CDR Example

Ref Clock for

Frequency Synthesis PLL

• Generally, we care about the jitter w.r.t. the ref. clock (x)
• However, may be easier to measure w.r.t. delayed version of output clk
• Due to noise on both edges, this will be increased by a sqrt(2) factor
to the reference clock-referred jitter
relative 39
Converting Phase Noise to Jitter
[Mansuri]

œ
8
• RMS jitter for T accumulation 2
𝜎OT = 2ƒ 𝑆$ 𝑓 𝑠𝑖𝑛 2
𝜋𝑓Δ𝑇 𝑑𝑓
𝜔
o 0

• As T goes to ∞  2  2
R 0 
2
T  S  f df o2 0
 o2  
• Actual integration range depends on application bandwidth
• fmin set by assumed CDR tracking bandwidth
• fmax set by Nyquist frequency (f0/2)
f0
2 2
• Most exact approach  T2   S  f
H sys  f 
 o2 0
 2
2
df
where H sys  f  is the system jitter transfer 40
function
 112Gb/s PAM4 PLL Phase Noise Measurement
Measured Phase Noise at 28GHz TX Output
<100fs Integrated RJRMS

-60
Phase Noise (dBC/Hz)

-80

-
100

-120 EL1

EL1
-140

LoopB W3 kHz

1e6 1e7 1e8 1e9 1e10

Frequency Offset (Hz)
[Turker ISSCC 2019]
41
 PLL Linear Phase Model
ref
out

3dB = 1.47Mrad/s

out(s) out(s)
20log 10 20log 10
ref(s) vcon (s)

42
PLL Linear Phase Model:
Frequency Step Response
ref
out

(s)= s=2  Mrad/sec

Frequency Step Input:  ref 32s2

No Cycle Slips Observed

with Linear Model

43
 PLL Behavioral Model
• From my MSc thesis:
http://www.ece.tamu.edu/~spalermo/docs/msc_thesis_sam_palermo.pdf
• Written in SpectreHDL
• Also look at CppSim: http://www.cppsim.com/
timedom tran stop=20u step=20p ic=all maxstep=20p skipdc=yes relref=alllocal
// Multi-Band Phase Locked Loop Frequency Synthesizer Macromodel
simulator lang=spice
// Main Spectre File
.ic vd=0
// Samuel Palermo
save vd control fref fvco nv_temp vd_gnd
simulator lang=spectre
.OPTIONS rawfmt=psfbin save=selected diagnose=yes vabstol=.01
include "/home/samuel/research/pll/macromodels/pd/dig_pfd/dig_pfd.def"
+ reltol=.99
include "/home/samuel/research/pll/macromodels/lpf/lpf.def"
ahdl_include "/home/samuel/research/pll/macromodels/vco/vco.def" ***********************************************************************
ahdl_include "/home/samuel/research/pll/macromodels/vco/switch_vco.def" // Digital Phase Frequency Detector Macromodel
ahdl_include // Samuel Palermo
+ "/home/samuel/research/pll/macromodels/divider/divider.def" subckt dig_pfd (gnd dd fref fvco up upbar down downbar)
include "/home/samuel/research/pll/macromodels/vco/reference.def" ahdl_include "/home/samuel/research/pll/macromodels/pd/dig_pfd/dff.def"
// Power Supply ahdl_include
vdd dd 0 vsource dc=1 + "/home/samuel/research/pll/macromodels/pd/dig_pfd/nand.def"
// Reference Signal xdffup gnd dd fref up upbar r dff
xref 0 control fref reference xdffdown gnd dd fvco down downbar r dff
vcontrol control 0 vsource type=pwl wave=[0 0.64 1u 0.64] xnand gnd up down r nand
// Digital Tri-State Phase/Frequency Comparator ends dig_pfd
xdig_pfd 0 dd fref fvco up upbar down downbar dig_pfd
// Charge Pump
****************************************
iup dd 1 isource dc=25u *******************************
idown 2 0 isource dc=25u // D Flip Flop Macromodel
gup 1 vd up 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m // Samuel Palermo
gupbar 1 0 upbar 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m module dff(gnd, D, CLK, Q, QBAR, R) ()
gdown vd 2 down 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m node [V, I] gnd, D, CLK, Q, QBAR, R ;
gdownbar dd 2 downbar 0 relay vt1=0 vt2=1 ropen=100M {
rclosed=1m real Q_temp;
// Loop Filter real QBAR_temp;
xfilter 0 vd lpf initial {
gvdgnd vd 0 Q_temp=0;
vd_gnd 0 relay QBAR_temp=1;
vt1=0 vt2=1 }
ropen=100M analog {
rclosed=10 if ($threshold (V(CLK, gnd)-1, 1)) {
// Voltage if (V(D,gnd)==1) {
Controlled Q_temp=1;
Oscillator QBAR_te
//xvco vd out vco (gain=40e6 fc=256e6) mp=0;
xvco 0 vd out nv_temp vd_gnd }
+ switch_vco (u=0.8 d=-0.8 gain=40e6 else {
fc=256e6) Q_temp=0;
// Divider QBAR_temp=1;
xdivider 0 out fvco buffer n_temp divider (divisor=32) }
op dc }
if (V(R,
gnd)==0) 44
{
Q_temp=0;
PLL Frequency Step Response:
Linear vs Behavioral Model

(s)= s=2  Mrad/sec

Frequency Step Input:  ref 32s2

No Cycle Slips Observed

with Linear Model

Cycle Slips

45
Next Time
• CDRs

• The following slides provide more details

on PLL circuits. This 620 material may
useful for the project, but won’t be covered
in detail on Exam 2.

46
 Open-Loop PLL Transfer Function

[Mansuri]

ignoring C1: (2nd order)

with C1: (3rd order)

47
Open-Loop PLL Transfer Function
w/o C1 (2nd order) with C1 (3rd order)

[Mansuri]

48
Closed-Loop PLL Transfer Function

[Mansuri]

ignoring C1:

49
PLL Natural Frequency and Damping Factor

Standard 2nd-order denominator: s 2  2ns  2

n


Natural Frequency:

Damping Factor:

Loop Bandwidth: 3dB  n a  a 2 1

2
 1

a  2 2 1 n N  4  n N 

K PD K VCO  K PD VCO 

K 50
Damping Factor Impact

[Fischette]

• If damping factor is too low, frequency peaking occurs

• Damping factor ~1 is usually preferred
• Excessively high damping also causes peaking
• Need 3rd order model to observe this
51
Damping Factor Impact
(s)=  2
Frequency Step Input:  ref
s
 = 0.1

 = 0.5

 = 0.707
=1
=2

KPD = 25uA/2
K VCO = 240MHz/V
N = 32
n = 1 (normalized)

• Peaking in frequency domain leads to ringing in the time

domain

52
Charge-Pump PLL Circuits
• Phase Detector
• Charge-Pump
• Loop Filter ref out

• VCO fb

• Divider

53
Phase Detector

e
ref

fb

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output, thus to characterize
phase detector gain, extract average output voltage (or current for
charge-pump PLLs)
54
Analog Multiplier Phase Detector
A1 cos1t
A1 A1
cos1  2 t  
2 2
cos1  2 t  
A2 A2
  
A2 cos2t  
 is mixer gain

• If 1=2 and filtering out high-frequency term
A A
yt   1 2 cos
2
 A1 A2  
• Near  lock region of /2: y t   
 2  2  

K PD   A1 A2
2

[Razavi]
55
XOR Phase Detector

[Razavi]

• Sensitive to clock duty cycle

56
XOR Phase Detector

Width is same for both

leading and lagging
phase difference! [Perrott]

57
Cycle Slipping
• If there is a frequency difference between the input
reference and PLL feedback signals the phase detector can
jump between regions of different gain
• PLL is no longer acting as a linear system

[Perrott]

(positive feedback operation) (negative feedback operation)

58
Cycle Slipping

Cycle Slipping

[Perrott]

• If frequency difference is too large the PLL may not lock

59
Phase Frequency Detector (PFD)
• Phase Frequency Detector allows
for wide frequency locking range,
potentially entire VCO tuning range
• 3-stage operation with UP and
DOWN outputs
• Edge-triggered results in duty cycle
insensitivity

60
PFD Transfer Characteristic
UP=1 & DN=-1

[Perrott]

• Constant slope and polarity asymmetry about zero

phase allows for wide frequency range operation
61
PFD Deadzone
• If phase error is small, then short output pulses are produced by PFD
• Cannot effectively propagate these pulses to switch charge pump
• Results in phase detector “dead zone” which causes low loop gain and
increased jitter
• Solution is to add delay in PFD reset path to force a minimum UP and
DOWN pulse length

[Fischette]
62
PFD Operation

Min. Pulse Width

[Fischette]
63
Charge-Pump PLL Circuits
• Phase Detector
• Charge-Pump
• Loop Filter
• VCO
• Divider

64
Charge Pump
VDD

I
Charging VCO Control
UP
Voltage

C1 C2
DOWN Discharging
I R

VSS

• Converts PFD output signals to charge

• Charge is proportional to PFD pulse widths
PFD-CP Gain:  1  I CP
 2  65
Simple Charge Pump

[Razavi]

• Issues
• Switch resistance can impact UP/DN current matching as a function of Vctrl
• Clock feedthrough and charge injection from switches onto Vctrl
• Charge sharing between current source drain nodes’ capacitance and Vctrl

66
Charge Pump Mismatch
Ideal locked condition, but CP mismatch Actual locked condition w/ CP mismatch

[Razavi]
• PLL will lock with static phase error
• Extra “ripple” on Vctrl
• Results in frequency domain spurs at the reference clock frequency
offset from the carrier
67
Charge Pump w/ Improved Matching

[Young JSSC 1992]

• Amplifier keeps current source Vds voltages constant

resulting in reduced transient current mismatch
68
Charge Pump w/ Reversed Switches
• Swapping switches
reduces charge injection
• MOS caps (Md1-4) provide
extra charge injection
cancellation

• Helper transistors Mx and

My quickly turn-off current
source

• Dummy brand helps to

[Ingino JSSC 2001]
match PFD loading

69
Charge-Pump PLL Circuits
• Phase Detector
• Charge-Pump
• Loop Filter
• VCO
• Divider

70
Loop Filter
VDD

I
Charging VCO Control
Voltage

C1 C2
Discharging
I R
F(s)
VSS

• Lowpass filter extracts average of phase

detector error pulses
71
Loop Filter Transfer Function
• Neglecting secondary capacitor, C2

72
Loop Filter Transfer Function
• With secondary capacitor, C2

73
Why have C2?
• Secondary capacitor smoothes control voltage ripple
• Can’t make too big or loop will go unstable
• C2 < C1/10 for stability
• C2 > C1/50 for low jitter

Control Voltage Ripple

74
Filter Capacitors
• To minimize area, we would like to use highest density caps
• Thin oxide MOS cap gate leakage can be an issue
• Similar to adding a non-linear parallel resistor to the capacitor
• Leakage is voltage and temperature dependent
• Will result in excess phase noise and spurs

• Metal caps or thick oxide caps are a better choice

• Trade-off is area

• Metal cap density can be < 1/10 thin oxide caps

• Filter cap frequency response can be relatively low, as PLL
loop bandwidths are typically 1-50MHz

75
Charge-Pump PLL Circuits
• Phase Detector
• Charge-Pump
• Loop Filter
• VCO
• Divider

76
Voltage-Controlled Oscillator

KVCO
0 1

VDD/2

VDD

out t Laplace
  0   out t    0  KVCO vc
Domain Model
out t    out t dt  KVCO  vc t t 
• Time-domain
dt phase relationship
out(t)

77
Voltage-Controlled Oscillators (VCO)
• Ring Oscillator
• Easy to integrate
• Wide tuning range (5x)
• Higher phase noise

• LC Oscillator
• Large area
• Narrow tuning range (20-30%)
• Lower phase noise

78
 Barkhausen’s Oscillation Criteria

[Sanchez]

H  j
Closed-loop transfer function:


• Sustained oscillation occurs1ifH  Hj j 

 1

• 2 conditions:
• Gain = 1 at oscillation frequency 0
• Total phase shift around loop is n360 at oscillation frequency 0
79
Ring Oscillator Example
[Sanchez]

80
 Ring Oscillator Example

• 4-stage oscillator
• A0 = sqrt(2)
• Phase shift = 45

• Easier to make a
larger-stage
oscillator oscillate, as
it requires less gain
and phase shift per
stage

[Sanchez]

81
LC Oscillator Example
• Oscillation phase shift condition
satisfied at the frequency
when the LC (and R) tank load
displays a purely real
impedance, i.e. 0 phase shift

LC tank impedance
RS  L1s
Z eq s
1 L C s 2  R C s
 1 1
S
1
2  L12
Z eq
s  j   1 R S2
LC
2 2
2
 R
2 2 2
S 1
C1 1
LC Oscillator Example
• Transforming the series loss
resistor of the inductor to an
equivalent parallel
resistance

 2S  2 2
LP  L1 1 2 2 , CP  C1, R  1 L 
 R
 L1  P RS
RP 

1
1  [Razavi]
LPC P
83
LC Oscillator Example
Loop Gain
[Razavi]

1
• Phase condition satisfied at 1 
LPC P
• Gain condition satisfied when g m RP  
1
2

• Can also view this circuit as a parallel

combination of a tank with loss resistance
2RP and negative resistance of 2/gm
• Oscillation is satisfied when
1
gm  R
P

84
Supply-Tuned Ring Oscillator

[Sidiropoulos VLSI 2000]

2nC stage
TVCO  2nTD 
 Vc Vth

KVCO  fVCO 
Vc 2nCstage
85
Current-Starved Ring Oscillator

[Sanchez]

86
Capacitive-Tuned Ring Oscillator

87
Symmetric Load Ring Oscillator
[Maneatis JSSC 1996 & 2003]

• Symmetric load provides frequency tuning at excellent

supply noise rejection
• See Maneatis papers for self-biased techniques to obtain
constant damping factor and loop bandwidth (% of ref clk)
88
LC Oscillator
• A variable capacitor
(varactor) is often used to
adjust oscillation frequency

• Total capacitance includes

both tuning capacitance and
fixed capacitances which
reduce the tuning range
1
1
osc  LP C P  LP 
Ctune  C fixed

89
Varactors
• pn junction varactor
• Avoid forward bias region to prevent oscillator nonlinearity

• MOS varactor [Perrott]

• Accumulation-mode devices have better Q than inversion-mode

n-well
[Razavi]
90
Charge-Pump PLL Circuits
• Phase Detector
• Charge-Pump
• Loop Filter
• VCO
• Divider

91
 Loop Divider

out(t) fb(t)

[Perrott]

• Time-domain model
 fb t   1 out t
N

 fb t   N1  t dt N1  t
out out

 92
Basic Divide-by-2
[Perrott]

• Divide-by-2 can be realized by a

flip-flip in “negative feedback”

• Divider should operate correctly

up to the maximum output clock
frequency of interest PLUS
some margin
[Fischette] 93
 Divide-by-2 with TSPC FF
True Single Phase Clock Flip-Flop
Divider Equivalent Circuit
Note: output inverter not in left schematic

• Advantages
• Reasonably fast, compact size, and no static power
• Requires only one phase of the clock
• Disadvantages
• Signal needs to propagate through three gates per input cycle
• Need full swing CMOS inputs
• Dynamic flip-flop may have issues at very low frequency operation (test
mode) depending on process leakage
94
Divide-by-2 with CML FF

[Razavi]

• Advantages
• Signal only propagates through two CML gates per input cycle
• Accepts CML input levels
• Disadvantages
• Larger size and dissipates static power
• Requires differential input
• Need tail current biasing
• Additional speedup (>50%) can be achieved with shunt peaking
inductors 95
 Binary Dividers:
Asynchronous vs Synchronous
Asynchronous Divider • Advantages
• Each stage runs at lower frequency,
resulting in reduced power
• Reduced high frequency clock
loading
• Disadvantage
• Jitter accumulation
Synchronous Divider
• Advantage
• Reduced jitter
• Disadvantage
• All flip-flops work at maximum
frequency, resulting in high power
• Large loading on high frequency
clock
[Perrott]
96
 Jitter in Asynchronous vs Synchronous Dividers
Asynchronous • Jitter accumulates with the
clock-to-Q delays through
the divider
• Extra divider delay can also
degrade PLL phase margin

Synchronous • Divider output is “sampled”

with high frequency clock
• Jitter on divider clock is
similar to VCO output
• Minimal divider delay
[Perrott]

97
Dual Modulus Prescalers
2/3

MC=0  3
MC=1 
2

15/16

[Razavi]

Synchronous 3/4 Asynchronous 4

• For /15, first prescaler circuit divides by 3 once and 4 three times
during the 15 cycles
98
 Injection-Locked Frequency Dividers
LC-oscillator type (/2) Ring-oscillator type (/3)

[Verma JSSC 2003, Rategh JSSC 1999] [Lo CICC 2009]

• Superharmonic injection-locked oscillators (ILOs) can
realize frequency dividers
• Faster and lower power than flip-flop based dividers
• Injection locking range can be limited
99
Example PLL Design Procedure
• Design procedure for a 100-300MHz frequency synthesizer
• Step 1 – Determine VCO Tuning Range
• Needs to be at least the output frequency range plus some margin
(10-20%) dependent on PVT tolerance
VCO Tuning Range  100 - 300MHz *
• *Note if you want the frequency extremes (100 or 300MHz)
you probably want to add some margin here
• Step 2 – Determine Loop Division Ratio, N
• This is a function of what reference clocks you have access to,
loop bandwidth, dominant noise sources
N  32
• Step 3 – Determine Damping Factor
• Damping factors between 0.5 and 2 are reasonable, with 0.7 or 1
commonly chosen
  1  0.707
2 100
Example PLL Design Procedure
• Step 4 – Determine natural frequency, n
• This is a function of the desired loop bandwidth and also the
damping factor
• Maximum loop bandwidth should be less than 1/10th the
input reference clock for the loop to act as a
continuous- time system
100MHz
Lowest Input Reference Frequency  32  3.125MHz
• Set the loop bandwidth with some margin - 75% of max value

3dB  0.752 312.5kHz  1.47

Mrad

• For a damping factor of 0.707

s
1.47 Mrad krad
 n  3dB s
2.06  2.06 s  714

101
Example PLL Design Procedure
• Step 5 – Determine KVCO K vco = 40MHz/V
300
Channel 4 (235 - 300MHz)

Frequency (MHz)
255
• This is a function of the VCO and 235
210
Channel 3 (190 - 255MHz)

Channel 2 (145 - 210MHz)

charge pump operating voltage 190

145
165
Channel 1 (100 - 165MHz)

range 100
Voltage Range = 1.6V
• Here I use a combination of VCO Control Voltage

discrete tuning caps, resulting in

K VCO  2 65MHz  255 Mrad
multiple frequency bands over the
total frequency range 1.6V sV

• Step 6 – Determine Charge Pump Current & Filter Cap

Set I  25A

25A 255 Mrad

sV

C1 
  62.2 pF
2
2 32  krad 
 s 
714 
• Step 7 – Determine Filter R and Secondary Cap
2 20.707
R   31.8k C1
C2   6.22 pF  C 
2 6 pF
 714 s 62.2 pF
 n C1  krad 
10

102