Instruction Set

Architecture
Instruction sets are differentiated by the following:

•Number of bits per instruction

•Stack-based or register based.
•Number of explicit operands per instruction
•Operand location
•Types of operations
•Type and size of operands
 ISA are measured according to

•Main memory space occupied by a program

•Instruction complexity
•Instruction length (in bits)
•Total number of instructions in the
instruction set
In designing an instruction set, consideration is given to

•Instruction length
• Whether short, long, or variable
•Number of operands
•Number of addressable registers
•Memory organization
• Whether byte-word addressable
•Addressing modes.
• Choose any or all: direct, indirect or
indexed
 Memory Organization

• Memory Consists of many millions of

storage cells.
• Each cell can store a bit of information
having the value of 0 or 1.
• Bits are group into a fixed size.
• Each group of n bits is referred to as a word
of information, and n is called the word
length.
Memory Organization

n bits
First word
Second word
..
.
ith word
...
last word
 Memory Organization

• Memory Consists of many millions of storage

cells.
• Each cell can store a bit of information
having the value of 0 or 1.
• Bits are group into a fixed size.
• Each group of n bits is referred to as a word
of information, and n is called the word length.
• Modern computers have word lengths that
typically range from 16 to 64 bits.
 Memory Organization

32 bits
b31 b30 b1 b0

Sign bit: b31 = 0 for positive numbers

b31 = 1 for negative numbers

A signed integer
 Memory Organization

32 bits
8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

Four characters
 Memory Organization

• Accessing the memory to store or retrieve a

single item of information, either a word or a
byte, requires a distinct names or addresses
for each location.
• Memory can have up to 2k addressable
locations.
• 2k addresses constitute the address space of
the computer.
• example, 24 bit address generates an
address space of 224 (16,777,216) locations.
 Byte Addressability

• We now have three basic information

quantities to deal with: bit, byte, and word.
• byte is always 8 bits
• word length typically ranges from 16 to 64
bits.
• It is impractical to assign distinct addresses
to individual bit location in memory.
• Most practical assignment is to have
successive addresses refer to successive byte
locations in the memory
 Byte Addressability

• Most modern computers used byte-

addressable memory for this assignment.
• Byte location have addresses 0, 1, 2, ….
• For the word length of 32 bits, successive
words are located at addresses 0, 4, 8, …. with
each word consisting of four bytes.
• There are two ways that byte addresses can
be assigned across the words: Big-endian and
Little-endian
 Byte Addressability

• big-endian is used when lower byte

addresses are used for the more significant
bytes (the leftmost bytes) of the word.

Word Byte address

address
0 0 1 2 3
4 4 5
.. 6 7

2k-4 2k-4 2k-3 2k-2 2k-1

 Byte Addressability

• little-endian is used for the opposite

ordering, where the lower byte addresses are
used for the less significant bytes (the
rightmost bytes of the word.
Word Byte address
address
0 3 2 1 0
4 7 6
.. 5 4

2k-4 2k-1 2k-2 2k-3 2k-4

 Byte Addressability

• The words “more significant” and “less

significant” are used to the weighs (powers of
2) assigned to bits when the word represents a
number.
• The little-endian and the big-endian
assignments are used in commercial
machines.
 Byte Addressability

•Big endian:
• Is more natural
• The sign of the number can be determined by
looking at the byte at address offset 0
• Strings and integers are stored in the same order

•Little endian:
• Make it easier to place values on non-word
boundaries
• Conversion from a 16 bit integer address to a 32
bit integer address does not require any
arithmetic
•The next consider for architecture design concerns
how the CPU will store data
•We have three choices
• A stack architecture
• An accumulator architecture
• A general purpose register architecture
•In choosing one over the other, the tradeoffs are
simplicity (and cost) of hardware design with
execution speed and ease of use.
•In a stack architecture, instructions and operands
are implicitly taken from the stack
• A stack cannot be accessed randomly
•In an accumulator architecture, one operand of a
binary operation is implicitly in the accumulator
• One operand is in memory, creating lots of bus
traffic
•In a general purpose register (GPR) architecture,
registers can be used instead of a memory,
• Faster than accumulator architecture
• Efficient implementation for compilers
• Results in longer instructions
 Memory Operations

• Both Program instructions and data

operands are stored in the memory.
• To execute an instruction, word containing
the instruction must be transferred from the
memory to the processor.
• Operands and results must also be moved
between the memory and the processor.
• two basic operations involving the memory:
Read and Write.
 Memory Operations

• Read operation transfer a copy of the

contents of a specific memory locations to the
processor.
• Write operation transfers an item of
information from the processor to a specific
memory location.
Instructions and Instruction Sequencing

• Computer program tasks consist of a

sequence of small steps, like adding two
numbers, testing a particular condition, etc.
• Computer must have instructions capable of
performing four types of operations:
• Data transfer between the memory and
the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
Instructions and Instruction Sequencing

• Register Transfer Notation

• we need to describe the transfer of
information from one location in a
computer to another.
• possible locations are memory,
processor registers, or registers in the
I/O subsystem.
Instructions and Instruction Sequencing

• Register Transfer Notation

• consider the following expression:
R2 [LOC]
means that the contents of memory
location LOC are transferred into
processor register R2.

Note: the content of any location are

denoted by placing square brackets
around its name.
Instructions and Instruction Sequencing

• Register Transfer Notation

• another example:
R4 [R2] + [R3]
means that the contents of processor
registers R2 and R3 are added and places
their sum into processor register R4.

• In computer jargon, the term “transfer”

and “move” means “copy”.
Instructions and Instruction Sequencing

• Assembly-Language Notation
• another type of notation to represent
the machine instructions and programs.
• consider the previous example:
Load R2, LOC

The Load operation reads the content of

memory location LOC and copied into
processor register R2.
Instructions and Instruction Sequencing

• One of the most important characteristics

that distinguish different computers is the
nature of their instructions.
• There are two fundamentally different
approaches in the design of instruction sets
for modern computers. The first is Reduced
Instruction Set Computers (RISC) and the other
one is Complex Instruction Set Computers
(CISC)
Reduced Instruction Set Computers (RISC)

• The key two characteristics of RISC

instruction sets are:
• Each instruction fits in a single word.
• A load/store architecture is used, which
• Memory operands are accessed only
using Load and Store instructions
• All operands involved in an arithmetic
and logic operation must either be in
processor registers, or one of the
operands may be given explicitly within
the instruction word.
Reduced Instruction Set Computers (RISC)

• Load instructions are of the form

Load destination, source

More specifically

Load processor_register, memory_location

Reduced Instruction Set Computers (RISC)

• Consider the high-level language program

that add two variables called A and B, and
assign the sum to the third variable, C.
C = A + B
It requires the action
C [A] + [B ]

The required action can be accomplished by a

sequence of simple machine instructions.
Reduced Instruction Set Computers (RISC)

C [A] + [B ] is equivalent to four

instructions (let choose to use R2, R3, R4 to
perform the tasks):

Load R2, A
Load R3, B
Add R4, R2, R3
Store R4, C
Reduced Instruction Set Computers (RISC)

Add R4, R2, R3

Add is a three-operand, or a three-address,
instruction of the form

Add destination, source1, source2

Store R4, C
Store instruction is of the form
Store source, destination
Complex Instruction Set Computers (CISC)

• One key difference is that CISC instruction

sets are not constrained to the load/store
architecture
• arithmetic and logic operations can be
performed only on operands that are in
processor registers.
• Another key difference is that instructions
do not have to fit into a single word. Some
instruction may occupy a single word, but
others may span multiple words
Complex Instruction Set Computers (CISC)

• Instruction in modern CISC processors

typically do not use a three-address format
• Most arithmetic and logic instructions use
the two-address format
Operation destination, source

•Lets consider again the expression

C= A + B
Complex Instruction Set Computers (CISC)

C = A + B

can be perform in CISC as:

Move C, B
Add C, A
Complex Instruction Set Computers (CISC)

• In some CISC processors one operand may

be in the memory but the other must be in a
register. In this care, the instruction sequence
for the required task would be
Move Ri, A
Add Ri, B
Move C, Ri

• The general form of the Move instruction is

Move destination, source