ARM- Instruction Set -1

M3: Embedded Architectures- 1: RISC Architecture - ARM

Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte
• Mode3: Load/Store half-word/signed byte

RL 3.2.1 Embedded System Design © K.R.Anupama &

• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor

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31-28 27 26 25 24-21 20 19-16 15-12 11-0

Cond 0 0 I opcode S Rn Rd Operand 2

ADD {condn} {S} Rd, Rn, <Oprnd2>

EQ #32 bit
NE Rm LSL #5bit
CS Rm LSR #5bit
CC

RL 3.2.1 Embedded System Design © K.R.Anupama &

Rm ASR #5bit
MI
Rm ROR #5bit
PL
Rm
VS
Rm LSL Rs
VC
HI Rm LSR Rs

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LS Rm ASR Rs
GE Rm ROR Rs
LT
No Condition Taken as AL
LE
AL 3
ADD R2, R2,#1
ADD R4,R5, R5, LSL #2
ADD R10,R15,#8
ADDS R4,R5,R6, LSR R7

R4 = 00 00 00 02 + 00 00 00 10

RL 3.2.1 Embedded System Design © K.R.Anupama &

R2 = 20 02 10 55 R2 = 20 02 10 56
R10 = 00 A0 B1 08
R5 = 00 00 00 02
R4 = 00 00 00 02 + 00 00 00 08
R15 = 00 A0 B1 00

R6 = 00 00 00 02

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R7 = 00 00 00 03

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Arithmetic & Logical
Instructions
Arithmetic Logical
• ADD • AND

RL 3.2.1 Embedded System Design © K.R.Anupama &

• ADC • ORR
• SUB • EOR
• SBC • BIC
• RSB
• RSC

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31-28 27 26 25 24 23 22 21 20 19- 15- 11-0
16 12
Cond 0 1 1 P U B W L Rn Rd Addr mode

LDR/STR {condn} {B} {T} Rn, Rd, <Addr Mode>

EQ
NE
CS
+/-
CC

RL 3.2.1 Embedded System Design © K.R.Anupama &

size
MI
PL
0 x post
VS
1 0 pre
VC
1 1 Pre+W
HI

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LS
GE
LT
LE
AL 6
LDR R1, [R0]
Address in R0
LDR R8, [R3, #4]
Address = [R3]
LDR R12, [R13, #-4] R3 = R3 +4
STR R2, [R1, #0x100] Address = [R13]
R13 = R13 -4
LDRB R5, [R9]
Address = [R1]
STRB R4, [R10, #0x200] R1 = R1 +0100H

RL 3.2.1 Embedded System Design © K.R.Anupama &

Address in R9
Address = [R10]
R10 = R10 +0200H

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 Address = [R1]
LDR R11, [R1, R2] R1 = R1 + R2
STRB R10, [R7, -R4] Address = [R7]
R7 = R7 + R4
LDR R11, [R3, R5, LSL #2]
Address = [R13]
LDR R1, [R0, #4]! R13 = R13 + R5 * 4
LDR R3, [R9], #4 R0 = R0 +4
Address = [R0]+4
STR R2, [R5], #8
LDR R0, [R1], R2 Address = [R9]+4

RL 3.2.1 Embedded System Design © K.R.Anupama &

STRB R7, [R6, #-1]!

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Transfer btwn memory & reg

LDR/LDRB/LDRH/LDRSH

STR/STRB/STRH/STRSH

ADR

RL 3.2.1 Embedded System Design © K.R.Anupama &

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